3D-IC of chip of much nakedder brilliant encloses TSMC of support of Design Platform of new Cisco ability technology

3D-IC of chip of much nakedder brilliant encloses TSMC of support of Design Platform of new Cisco ability technology

[introduction] new Cisco ability announces, design Platform of new Cisco ability supports TSMC WoW in the round direct pile and CoWoS® are advanced enclose a technology. Design Platform support and photograph of 3D IC referenced flow are united in wedlock, help user is in the application such as communication of mobile computation, network, consumption and car electron deploy joins high-poweredly, high chip of much nakedder brilliant technology.
3D-IC of chip of much nakedder brilliant encloses TSMC of support of Design Platform of new Cisco ability technology 
New Cisco ability (Synopsys, inc. ) announce, design Platform of new Cisco ability supports TSMC WoW in the round direct pile and CoWoS® are advanced enclose a technology. Design Platform support and photograph of 3D IC referenced flow are united in wedlock, help user is in the application such as communication of mobile computation, network, consumption and car electron deploy joins high-poweredly, high chip of much nakedder brilliant technology.
 
Solution of Design Platform of new Cisco ability includes chip of much nakedder brilliant and intermediary layer domain to found, analysis of extraction of parameter of physical distribution program and design implementation, parasitism, sequential and physical test and verify. TSMC WoW of support of Design Platform of new Cisco ability and CoWoS are advanced the main product that encloses a technology and character include:
 
IC Compiler™II layout wiring: Support program of distribution of chip of much nakedder brilliant and implementation, include intermediary layer and 3D brilliant round pile to generate, TSV layout is mixed join allocation, orthogonality 45 degrees of multilayer, monolayer, and each other of naked brilliant chip creates even interface module the parameter between is extracted and examine in order to be used at naked brilliant chip.
StarRC™ parameter extracts: Layer of intermediary of supportive TSV and extraction of layer of rear RDL metal, silicon is extracted, and extraction of capacitance of the coupling between naked brilliant chip.
IC Validator: The DRC between chip of DRC of supportive whole system and LVS test and verify, naked brilliant reachs interface LVS test and verify.
PrimeTime®Signoff analysis: Sequential of whole system static state is analysed, support sequential of static state of chip of much nakedder brilliant to analyse (STA)
Suk Lee of senior inspector general represents department of market of TSMC design infrastructure: Silicon chip of high-powered advanced 3D makes “ and technology of brilliant round pile needs brand-new EDA function and flow, in order to support higher design and complexity of test and verify. We strengthen the cooperation with new Cisco ability, the CoWoS that is TSMC and WoW are advanced enclose a technology to offer design solution. We believe, design solution will make bilateral client is benefited from which, improve the work efficiency that designs staff, accelerate a product to appear on the market.
 
Sale of ministry of career of design of chip of new Cisco ability and Michael Jackson of vice president of business affairs development express: “ cooperates through development, the WoW that supports TSMC and CoWoS chip are compositive the design solution of the solution and referenced flow will make our collective client achieves first-rate quality result. Design Platform of new Cisco ability can satisfy the plan that devises personnel to ask, the plan of chip of much nakedder brilliant that implements tall cost effectiveness, high-powered, low power comsumption. ”
 
 

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