Place of signal of the stray outside the belt causes mix the crucial question that folds the place in seeming A/D converter to apply now to be faced with, if do not have proper filter wave processing, these signal can affect data badly to change function target of the system. The article basically discusses fight the principle that mixes the wave that fold filter to reach its to be opposite the influence of systematic performance. The article is aimed at this one application, offerred filter of capacitance of a switch to design model, this plan has extremely high gender price to compare. The article covered all important parameter that concern with high-powered system design and real problem almost.

 

Generation mixes folded origin: This are in Nai Kui this gave out to explain in specific reason. Nai Kui this specific reason points out: When successive signal changes time into disperse signal, need the sampling time inside a cycle 2 times over. If sampling number is insufficient, will not restore missing information. From the graph 1 can see this more clearly, if signal is weekly period sampling, those who get is signal of a dc only (extent is worth) for random, if pursue,1a place is shown. If every are periodic sampling two, get signal of a square wave (graph 1b) .

 

Notable is: The sampling that has every cycle 2 times to inputting signal is a kind of very special situation, any moment should prevent this kind of situation. Graph 1c place is shown is the case that has sampling to 190kHz signal with 200kHz sampling rate. Earning signal is an in good condition sine wave, but frequency is a mistake. Because the change of frequency mixes those who fold a phenomenon to bring about.

 

Graph 1a. When the sampling that has every cycle to sine signal, the dc signal that gets an extent is aleatoric value.

 

Graph 1b. To same sine wave every cycle sampling two, get a square wave, extent information is missing.

 

Graph 1c. Fsignal = 190kHz, Fs = 200kHz is to owe sampling signal, earnings result is to mix those who fold a phenomenon to bring about.

 

The graph is shown 2 times is the expressional form in frequency domain, can see from inside the graph, the signal of F >fs/2 of frequency prep above is gone to by the mirror Fs/2. To avoid this kind of appearance, must assure to there is higher frequency component in signal. Accordingly, we must understand the highest frequency of signal, sampling frequency needs prep above double of this frequency. A kind of the most primitive consideration is from the number region solves this problem, but this cannot be taken apparently, because once finish signal sampling, some signal mix the frequency that folds place to be interested paragraph, cannot move from inside signal except these frequency component. Fight mix the wave that fold filter to must undertake in imitate region, it is namely before signal sampling.

 

Graph 2. Frequency domain is mixed mediumly fold a phenomenon, owe sampling signal mirror to arrive Fs/2.

 

Next—The design is fought mix fold filter. The design is fought mix the filter baud that folds filter to need to decide a hope above all quality (end frequency, transfer take the) such as attenuation, the plan of optimal filter wave that chooses to be able to satisfy applied requirement next (call filter type) sometimes. Usually, had used sampling, and over- sampling frequency is taller, filter design is easier. But, cross sampling to need the ADC of higher rate, cost is higher also. For example, cross sampling factor to be 8 when, sampling frequency is highest signal frequency is eightfold. This is mixed in ADC cost filter is complex it is better to spent a respect to achieve eclectic.

 

Hypothesis ADC resolution is 14, the letter a confusion of voices that can offer 80dB is compared (SNR) . The sampling that uses an in part is led (here is signal frequency 4 times) when, low the attenuation that connects filter to need to offer 80dB, in order to ensure all stray signal passes enough attenuation, in the signal that won’t appear after sampling. This is meant in transfer the attenuation that needs to offer 40dB of Cheng of every times frequency inside the belt, need high-ranking filter to achieve this to design a requirement. 7 rank filter can satisfy Batewosi afore-mentioned requirements, but be not optimal choice to specific applying. Can choose different filter type in the light of different application, the graph is shown 3 times for Batewosi the frequency of filter, Chebyshev filter and elliptical filter rings characteristic.

 

Can see from inside the graph, they have different bandpass, transfer the belt is characteristic. Filter photograph compares elliptical filter and Batewosi, the transition of elliptical filter is taken abrupter, but character of its photograph frequency is wronger. Answer to select filter kind according to specific applying, collect a system to average data, can choose Batewosi filter (or) of filter of Bei Sai Er, if be opposite if phasic precision demand is not high, also can choose Chebyshev, elliptical even filter.

 

Graph 3. The comparison that different filter frequency answers

 

General A/D converter has: The SAR (successive that is used at moderate rate is approached) the Σ-ΔADC that ADC; uses at high speed to go to those who exceed high speed rate to show fast ADC; to be used at low speed system. They need to fight mix fold filter, depend on to the requirement of filter the input bandwidth that changes hope of rate, place, but Σ-ΔADC is more special. Technology of this kind of changeover uses very tall input to sampling is led and change rate, after that filter wave reduced add number to take in and send out in large quantities effectively rate, this meeting affects resolution (dynamic limits) rise. Σ-ΔADC antagonism mixes the requirement that folds filter and input sampling rate and highest signal frequency than concerning, this kind to demand reduce also behave likewise sampling data converter passes in other in, simple RC filter can be chosen below this kind of circumstance. Choose simpler fight mix fold filter to be able to produce longer transmission delay time, this is use closed-loop control or the converter of multichannel changeover increased to design difficulty.

 

Because imitate filter has certain design difficulty and bigger common difference, and production difficulty, especially compact to the space product, a lot of design personnel are not willing to use imitate filter. A when measure an error better criterion is hypothesis detached component tolerance is double, such, if use standard business to use,change resistor and capacitor, will diagonally frequency and transfer belt cause very big error. The optimal way that solves this one problem is to choose compositive filter plan, can obtain this kind of chip from the company such as Maxim.

 

Compositive filter has two kinds of kinds: Consecutive time filter and switch capacitance filter, consecutive time filter needs exterior component to adjust normally horny frequency, limitted their flexibility thereby. Switch capacitance filter can be used neatly according to its structure, usually, can replace depart or filter of compositive and consecutive time.

 

Compositive filter has two kinds of kinds: Consecutive time filter and switch capacitance filter, consecutive time filter needs exterior component to adjust normally horny frequency, limitted their flexibility thereby. Switch capacitance filter can be used neatly according to its structure, usually, can replace depart or filter of compositive and consecutive time. Switch capacitance filter is the filter construction that a kind of early is approved by people, use current silicon engineering technology can reliable and compositive. Its job principle and mathematical derivation are shown 4 times like the graph.

 

Working principle is: In capacitor the switch control of two end falls, capacitance is charged, discharge. This kind of charge transfers a process to produce pulse electricity, can calculate its are average electric current, when switch frequency enough fast when, equivalent of this electric current passes the electricity of resistor at flowing, can be being regarded is resistor is replaced by place of a capacitance.

 

Electric current and indirect resistance depend on two elements: Capacitance size and switch frequency. Value of taller, capacitance jumps over switch frequency big, criterion electric current is bigger, perhaps say, resistance is less. If use structure of this kind of filter, frequency character will be changed as the change of capacitance dimension or switch frequency. In compositive plan, capacitance value is fixed, filter baud sex gets the control of switch frequency. The principle of this kind of filter is shown 5 times like the graph.

 

Graph 4. Block diagram of switch capacitance principle

 

Graph 5. Use switch capacitance technology to make simple filter

 

The precision of filter depends on the tolerance of each component, in separate plan, we can use the cell with abhorrent tolerance only. And in compositive plan, can assure very tall component consistency () of 0.1% less than. Accordingly, we can control the frequency noisy character of compositive filter well. For example, the horny frequency precision of MAX7490 can be achieved 0.2% , and use detached component to cannot reach this one target. Additional, compositive plan still has outstanding temperature character, wen Piao coefficient can achieve 10ppm/°C.

 

Still need here special point out switch capacitance plan is right the sampling of signal, it time successive signal is changed into time disperse signal, this means us to consider to mix again even fold a problem. Those who be worth to rejoice is, the sampling rate of this kind of filter is very high, it is normally of 100 times cross sampling. So, need to use a simple block to allow filter only. The issue that the another in the system needs to consider is: Of switch clock phasic shake what what produce is lack fidelity, the question that exists in this and ADC is same. Graph 6 gave out to convincing sign by the circumstance of wrong sampling, can cause certain extent error.

 

Graph 6. Owe the magnitude distortion that sampling causes

 

Clock shakes have form of two kinds of expression, if phasic error is random, noise radical is low if will elevatory; shakes it is periodic, lack fidelity (THD) will increase. Shaking is quantity of a time, for example: Ps peak peak value or RMS. To achieve certain signal purity, can concessional and how old shake? 1 middle finger gives bibliographical reference, to a 16 system, peak value of 1nspp (peak) clock shakes can make SNR falls from 98dB to 91dB. To limit shaken influence 0.5dB, shake cannot prep above 400pspp. Use business to be able to satisfy afore-mentioned shaking easily with the clock oscillator that change the requirement of index, be like: SaRonix NTH5, shake have 8psRMS(53pspp) only. The blemish of this kind of plan was to restrict signal frequency. In most system, other parts of an apparatus (wait like ADC, µC) also need to offer clock.

 

If these clock use other oscillator generation, these clock will be not synchronous, will cause other a lot of problem. MAX7375 or DS1085 can produce many clock, and each other are synchronous, it is better to can be offerred shake index (it is 160ps and 300ps) respectively, can achieve the signal purity of 90dB above. Using this kind of parts of an apparatus to provide another benefit of clock is: But the clock frequency with different process designing.

 

That is to say, can obtain have software but the imitate filter that process designing frequency answers character, establish an extremely flexible system thereby. Graph 7 it is a data that is based on afore-mentioned discussion to offer collects systematic program. ADC has 14 resolution and 200ksps sampling rate (MAX1067 series) . This parts of an apparatus is changed every time need 24 clock at least.

 

Fight mix folded filter to introduce MAX7418-21 series product, this series filter provides all sorts of filter kinds, wait like Beisaier, Batewosi, ellipse. Horny frequency setting is 1/100 FClk. The sampling that controls converter considering DSP (need) of a timer only, same clock can be used at filter and ADC, completely synchronous. Use DS1085 to produce clock, can get two clock, the 2nd clock can be used at DSP. DS1085 passes process designing of 2 lines interface, work to be able to install frequency afresh when different sampling rate when the system, with the function that differs with implementation of a PCB.

 

Graph 7. Block diagram of principle of data sampling system

 

The graph shows circuit 7 times, work in coordination between parts of an apparatus, can accepting on cost and complex degree. Another advantage is but process designing sex, provided huge flexibility, simplified to design already, also reduced cost.