Carry puts a design site of these 10 hole, a few had you encountered?

Carry puts a design site of these 10 hole, a few had you encountered?

[introduction] carry put output voltage not to arrive after this kind of bright hole of power source course walked, I chose course to be put to the carry of course, ha, such carry are put can output power source course eventually. Glad backside is one concealments the move such as large hole I:
 
1. carry puts the course of 10 hole to course
 
Carry put output voltage not to arrive after this kind of bright hole of power source course walked, I chose course to be put to the carry of course, ha, such carry are put can output power source course eventually. Glad backside is one concealments the move such as large hole I:
 
See course carries my commonly used some company puts the introduction of the product to course: “ high speed (> 50MHz) course supports to course operation amplifier work with the lower power source voltage, amplitude that is close to power supply course more and wider dynamic range. ” sees:
 
“ works with the lower power source voltage, amplitude that is close to power supply course more and wider dynamic range. ”
“ is close to the amplitude ” of power supply course more
“ is close to ” more
“ is close to ”
. . .
 
See the manual that rail transport puts a course:
 
Carry puts a design site of these 10 hole, a few had you encountered?
Carry puts a design site of these 10 hole, a few had you encountered?
 
Outputting voltage was not to arrive really the 5V of power source, why?
 
The output level that carry puts is OK the configuration that this plants below brief melt into:
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Because MOS canal has,guide electrify block, when had shed electric current, caused voltage drop, accordingly, when load is bigger, guide pressure fall bigger, output voltage cannot achieve orbit more.
 
Say so, course is put to rail transport is not complete can make output reachs power source value, when wanting to use, still need to see load and temperature (block of block of shadow fugleman electrify is worth) the relation will decide output can be achieved how old voltage.
 
Carry puts a design site of these 10 hole, a few had you encountered?
Carry puts a design site of these 10 hole, a few had you encountered?
 
2.Carry puts 10 hole cannot the input of oversight slants buy electric current
 
Designed a cent to press circuit, theoretic input 1V, output 2V, but be measured, always be much nearly 6, 100 7 MV. If this enters ADC of 12 3V span, but should eat off many 600. Dot solution?
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Original carry is put because TVS leakage current and pipe input slant,input end reversely buy electric current, brought about two inputs to carry existence input to slant buy electric current (and because do not have any parts of an apparatus and another parts of an apparatus exactly like, this is both the input slants buy electric current is endless still and identical) ; These two slant after buy electric current can form bias voltage together with exterior resistor, output back end, form an error. If you chose a carry that is based on BJT design to put unfortunately, it has bigger input to slant buy electric current, can cause very big hind class error. Following graphs carry this kind put, it is “ stops really at big, it is rank grass ” simply.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Assume below, two inputs that input end slant buy electric current is identical.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
To, carrying to the input for, ib+ brings bias voltage to be equal to almost 0, and to retrorse input end, the bias voltage that Ib- brings is equal to 350mV (when computation, hypothesis Vout ground connection, be equivalent to R1//R2) . Accordingly, of need is increasing a resistance to input end, will compensate retrorse input to carry brought error.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Place of preamble of no less than is narrated, input of photograph of positive and negative slants buy electric current is endless and identical, compensation can reduce maladjusted tension only, and input of photograph of positive and negative slants difference of buy electric current also calls maladjusted electric current. When undertaking high accuracy or small signal sampling, can choose use of small maladjusted electricity to put, because join compensation resistance, also took the place of a new noise source, want to be joined cautiously.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Slant buy electric current is one of main errors that carry puts, in the hole later, return the error source that can introduce the form after a few influences.
 
3. carry puts the PSRR that drops of 10 hole quickly
 
Becoming me is a dish bird engineer when, do carry to put a design to take no account of PSRR, after should hearing of PSRR, choose carry to put every time can control the luck that the choice on the foundation has taller PSRR to put in cost.
 
For instance this carry put PSRR to achieve 160dB:
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
According to computational formula:
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Although power source voltage produces change inside 4.5V-5.5V interval, power source puts the influence of output to have 10nV only to carry.
 
Very regrettablly, this index is the dc change that points to power source voltage, and the change that does not include communication of power source voltage (be like ripple) , in communication the circumstance falls, this index can produce very big aggravation. Spec. What mention inside is dc change only, communication change is in from the back inside graphic representation, usually, be not senior engineer to treat graphic representation is to slip to turn over the past slipperily.
 
If carry discharge road used switch power source, do not have again go if wave of Ou, filter is done very well, class inputs precision to be able to be affected by huge after. In light of, the communication PSRR that same money use puts.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
To the ripple of 500kHz switch frequency, PSRR+ aggravation arrives to have 50dB only, hypothesis ripple size is 100mV, so to hind the influence aggravation of class can achieve 0.3mV. For the application that collects to very much small signal, this error is not acceptability. Accordingly, some application setting is carrying discharge source entrance makes a low wave that connect filter even (notice resistor power comsumption and resistor thermal noise please) .
 
4. carry puts the increases in disorder compensation electric capacity of 10 hole
 
A ” of “ old engineer says to me before, feedback circuit increases an electric capacity, circuit won’t concussion. See “ concussion ” is so lofty the term that go up, I on the spot muddled forced, later all circuit and a small electric capacity, such ability Professional.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Till a day, I should magnify a 100kHz (luck is very good, frequency still is done not have too tall, otherwise feedback carry puts voltage to do not have a law to play) signal, also be go up according to experience a capacitance, next. . . It is normal that signal also is done not have again. . . Because, went up the signal to 100kHz became impedance of this capacitance feedback to be less than 200Ω only, cause enlarge coefficient change.
 
Like that, this still is not crucial, the problem depends on: Does true need compensate capacitance?
 
Above all, carry puts interior to be put in a the utmost (want it to achievement is RC low cause) , it can cause phasic change, the biggest arrive – 90° :
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
If raise a the limit again, it can is opposite again again phasic have a change, still can increase 90° greatly most:
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
So phasic arrived – 180° , what problem do this have? That is “ concussion ” . See voltage lose the gain that feedback carry puts:
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
When certain frequency the Aβ of annulus road gain on the dot is equal to 1, and phasic for – 180° when, at this moment, vout/Vin can become infinity, circuit was not stabilized. Accordingly, when exterior increase when 0 o’clock, carry is put can enter shake in certain frequency dot, bring the distributinging electric capacity on the foot for instance, pursue as follows:
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
At this moment, we go up a capacitance, be equivalent to introducing artificially at 0 o’clock, those who pull is phasic, pull, but, this distributinging capacitance is general very small, make Aβ of gain of its annulus road is equal to the position of 1 very far, on so remote frequency speck, carry is put early cannot work normally. And see manual this carry puts oneself to be in 100k when, what phasic surplus comparatives is tall, exceeded 90° , do not need completely to increase additional compensation electric capacity.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Accordingly, to particular case, want concrete analysis, cannot be worn to run by belt of ” of “ old engineer.
 
5. carry puts 10 hole be treated unjustly in all the model inputs limits
 
Had encountered a problem before, after class carry puts enlarge before, put by carry again follow into ADC, the signal that receives ADC is 0.3V-1.5V. The feeling is a very simple circuit, but from the back this carry that working voltage is 5V of only power source puts actual measurement, when partial board gets stuck to be controlled in output 1.5V, its output is worth and did not follow completely to input a value, and under the signal that compares 1.5V, follow to be no problem, but once be close to incorrect.
 
Of course, this problem went up the conference of hardware group, the result that discusses finally is: This carry puts “ have a problem, we should look for manufacturer wail dish, but we are Xx enterprises, not must not manage again we, such, we change the carry of an other company to put ” . Unfortunate is, we treated unjustly a carry to put, and did not find problem reason, fortunately, in did not make clear completely below the premise of the principle, we chance the carry that picked an OK and regular job is put.
 
Will view an index that this next carry put, carry puts in all the model inputs limits:
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Carry is put in all modular input limits is an interval that carry puts input voltage, of its token is carry is put can the interval of linear job, input voltage namely in all modular value is inside this interval, when inputting voltage happening to change, output voltage can linear happening changes.
 
To following circuit, because be put in negative feedback, basically can thinking positive inputs upright voltage and negative input to carry voltage is same a value, and when this carry is put in 5V power supply, its in all modular input limits is – 0.1V comes 1.5V. Accordingly, when inputting voltage to be controlled in 1.5V, carry is put exist cannot the circumstance that normal linear follows.
 
Why cannot follow? Will see circuit of enlarge of a dynatron, it also is one of component that carry puts, will undertake illustrate.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
When the Vb of the input produces change, ie can produce corresponding change as Vb, cause the change of Vc thereby, this follows namely. If Vb continues to increase, make when value of computation of Vc=Vcc-Ie X Rc is negative number, and actually Ie X Rc can not exceed Vcc, magnify circuit reachs saturation at this moment even electric current is turned over, bring about output voltage to secure or cut a peak or wait reversely.
 
6. carry puts 10 hole cannot of oversight pressure place rate
 
Make 1pps drive circuit, ≤5ns of requirement ascendant edge, the signal that FPGA outputs is put with carry follow after enhancing drive, discover ascendant edge short of asks. Why? Because did not consider a main index, pressure place rate. Pressure place leading is to point to: The input is rank when jumping signal, the exports ratio of voltage time change average of closed circuit amplifier. Input an ideal namely rank jump signal, output can be one carries slope signal, the climb rate of this signal is pressed namely place rate.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
See what this carry puts press place rate:
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Essential short of asks, 5ns can climb 20mV, so, ascendant edge is essential short of design requirement. How to do? Later period flying line added a pulse to enhance circuit.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Pulse enhances circuit C4 and R4, be equivalent to C4 of a differentiating circuit and RL (when C X RL far be less than pressure place rate time) increase a direct current block R4, make the signal edge on laden RL becomes more abrupt. Analyse:
 
A. Capacitance C4 and RL body part press circuit, the computation of the graph below the basis is formulary, the metabolic ratio of the voltage on C4 is equal to the voltage on RL to be worth.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
B. So ratio of change of hypothesis capacitance voltage is almost indeclinable inside 0-τ limits, the voltage above so laden RL also is almost changeless, once capacitance begins to charge (voltage happening changes) , the voltage of laden RL rises to acme. Write down for weaveform 1, pursue as follows.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
C. Charge in capacitance next whereabouts begins after the end, lead the issue that does not have voltage without change to solve, increase R4 of a dc block to maintain weaveform, it is a direct weaveform, namely primitive weaveform, write down for weaveform 2.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
D. After two weaveform close together, as a result of weaveform 1, the ascendant edge of 2 gets weaveform great increase, make synthesis undee thereby ascendant edge is able to improve.
 
7. carry puts the feedback resistance that is forgotten of 10 hole
 
To enlarge exterior drive capacity, general meeting increases to follow in last class circuit, carry of feedback of choice electric current is put – the output bandwidth that CFA increases carry to put. Very simple, regrettablly you are tone does not come out. Still see a picture first. Very simple, regrettablly you are tone does not come out. Still see a picture first.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Course of what power source, in all bandwidth of modular input limits, gain accumulating, belt carries ability, pressure place rate. . . My all considered, incorrect still?
 
Because, CFA and VFA (voltage feedback carry is put) different, the use that when reading, learns is put, basically the teacher is to take VFA to undertake citing is mixed explain. Next graphs are the model that CFA carry puts:
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
It and VFA distinction are, inputting end is no longer two empty is broken, turning over ZB of photograph input resistor is a very little value, but cannot consider as absolutely again 0; Gout of its open loop gain is very big no longer, approximate however 1; Its Z that cross block can consider as infinity.
 
Accordingly, of CFA follow the circuit model of circuit is as follows:
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Solution gives Aβ to be equal to:
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Its closed circuit gain is:
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
When doing not have feedback resistor ZF, a is approximated 1, ZF hasten is bordering on 0, aβ hasten is bordering on boundless, gain hasten is bordering on 0, follow with what want circuit is completely different, the “CFA that often says on the net namely does not add feedback resistor to do not have signal ” . (did not find this word, forgetting is to be in what where see, can see next CFA manual go up only the introduction of pair of feedback resistor)
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Accordingly, want to increase resistance of a feedback, circuit can work normally.
 
PS: Derivation computation has skill above, can undertake computational derivation from Aβ only, because the computational premise of CFA is,inputting resistor ZB instead is a very little value; Its Z that cross block can consider as infinity, so, should be in seeking the limit is to find an onefold variable, if undertake seeking the limit according to final expression, a function, 3 variable (ZF hasten is bordering on 0, ZB hasten is bordering on 0, z hasten is bordering on boundless) , do not have a law to play, pursue as follows.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
8. carry puts the AD620 of the invalidation of 10 hole
 
The time of the university is read in me, appearance uses the term that amplifier is case of a tall X absolutely, return in that common the time that 3 carry put carry of the cent that take difference, appearance is put is freeboard in all the model is restrained than, the pronoun of high temperature stability, two voltage difference decreases antipodal photograph, got a result, this is a good thing that collects EEG signal absolutely.
 
Because EEG signal scope is very little, the class before be being added magnifies, also do not cross 1V left and right sides, accordingly, time-tested also problem of it doesn’t matter. Want to do signal of an industry spot to detect later, abnormal. Still see a picture first:
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Collect 4-20mA electric current, get 1V-5V voltage is differred, enlarge 2 times junior ADC of the class after entering. To prevent resistor power comsumption exorbitant, r128, r129, 3 resistor used R130 the kind that paralell connection takes a cost, took 250Ω finally this value.
 
Analyse, positive input carries 2V-10V, accord with parts of an apparatus to input limits (VCC-1.4V) , turn over photograph input to carry 1V-5V, I added negaive electricity, that is to accord with more; See enlarge multiple next 2 times, vmax=10V, also accord with parts of an apparatus to output limits (VCC-1.4V) ; Multiple of power source, enlarge, go Ou does not have a problem etc. This is one appears pursue without any wrong principles, but actually, its meeting produces a mistake when tall input voltage is worth.
 
View next in-house principles, understood (here picks some materials on a hand, be not the in-house principle of AD620, actually appearance puts a principle about the same)
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Positive input voltage and the R2 that input voltage body to put interior in appearance now instead are in, and the voltage that undertakes outputting truly, reflect by V1out and V2out, change a word to say, the voltage cost that raises finally deuces it is two, one is offerred by V1out, it will be taller than V1, additionally one is offerred by V2out, it will be lower than V2.
 
See principle picture again, in 20mA when, vin+ achieved 10V, vin- is 5V, enlarge 2 times, in-house need is put to magnify Vin+ to 12.5V in appearance. This had exceeded appearance to put power supply voltage, accordingly, be absolutely cannot regular job.
 
9. carries the sampling time of the ADC that puts 10 hole is carried put be a burden on
 
ADC collects signal, when signal is stable, very accurate; When signal changes, data is not stable. Of course, ADC has sampling time, software engineer also knows, he was collected 10 times, after be being taken only 5, but data still has not stable state. Let hardware see circuit, hardware engineer says, circuit does not have a problem of course, it is completely from buckle over there others those who come, how do this have a problem in me?
 
See the index Tcycmin=500ns of ADC and Tacqmin=80ns first, this is a SAR ADC, speed can go up Mbps, still calculate quite fast. So, it is successive sampling 10, what use time also ability 10μs left and right sides.
 
Carry puts a design site of these 10 hole, a few had you encountered?
Carry puts a design site of these 10 hole, a few had you encountered?
 
And carry is put input output from signal, not be a process that does not have delay time, however a process that delay time still takes concussion, in the meantime, because,the time of this process still is met hind the PCB of class circuitry is designed and increase. Pursue as follows:
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
View the index that carry puts, when 4V, achieve 0.01% , time is 5.1μs, the fluctuant error that brings right now is 0.4mV, and inside 4V limits, a 1LSB of 16 ADC is 0.06mV. The error can be eaten off 6, 7 pile up a word, if be mixed plus distributinging capacitance,take line resistance, this time can increase further, stabilization period increases the level after making, bring about an error to become thereby more big.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Later, software engineer is moved low sampling rate, increased to collect time, the problem is able to solve.
 
10. carry puts the power comsumption that is forgotten of 10 hole
 
Had made a board card, power comsumption requirement is very strict, accordingly, after the design is finished, drew power source tree, calculated the power comsumption of every parts of an apparatus, did not exceed, cast next edition, debug, one electrify, power comsumption exceeds bid.
 
Check from the back, discovery is carry put moment of power comsumption calculative to appear problem, next graphs such carry put circuit to use 5.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Because be dc drive, in calculative moment, considered carry to put the static power comsumption of itself only, PD=15V X 4.2mA =63mW, will consider according to power comsumption of the biggest static state, power comsumption surplus returns more than sufficient.
 
Carry puts a design site of these 10 hole, a few had you encountered?
 
Actually, oversight a main power uses up a dot: Carry puts 15V of power supply voltage to output voltage (1V-4.5V) the voltage between is poor, put in carry entirely inside used up, according to the biggest consideration that press difference, a circuit uses up 140mW. Power of this kind of dissipation, never had considered before, so, all alternative oversight, when the demand that encounters insecurity of power comsumption requirement, the problem is exposed came out.
 
From the back correcting when, chose low voltage to put power supply to carry, reduced dissipation power comsumption, satisfied index requirement.
 
 

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