This circuit has good linear and precision, output is every second when 1000 pulse, the error has 1% only. If every second 10 pulse, its error can decrease 0.001% .

 

 

Because the cathode of SCR of commutator of silicon controlled rectifier is join,nod to the addition of operation amplifier. Should use negative voltage to control so. To inputting voltage to be able to pour the input after the photograph.

 

Circuit restoration is by R-S trigger and delay time fall implement will finish. At ordinary times end of trigger Q output is low n, SCR of reason silicon controlled rectifier ends, the output of integrator is added to the base of dynatron VT1 through diode VD1. When integrator output is achieved about 1.4V when, transistor guides, make trigger set. Right now the Q output of trigger becomes tall n, SCR of silicon controlled rectifier guides, integral capacitance discharges. The delay time of 1us of tall n classics that Q exports and make after the photograph trigger restoration, integral capacitance C discharges about 0.7V when, silicon controlled rectifier ends, then the 2nd integral cycle begins.