Electrostatic discharge (ESD: Electrostatic Discharge) , should be to cause all electrons yuan parts of an apparatus or integrated circuit system cause excessive report stress (EOS: The main prime culprit that Electrical Over Stress) destroys. Because electrostatic instantaneous voltage is very normally tall (> ) of thousands of bend over, so this kind of injury is annihilative and permanent, can cause circuit direct burn down. Preventing electrostatic damage so is all IC design and made number one difficult problem.

 

Electrostatic, be factitious generation normally, if produce, assemble, test, deposit, carry in waiting for a process, make likely electrostatic accumulate in human body, instrument or equipment, even yuan itself of parts of an apparatus also can be accumulated electrostatic, make below unwitting circumstance when people these electrified object contacts can form discharge way, the instant makes the damage that electronic component or system suffer electrostatic discharge (why do this repair computer to must want to deserve wear electrostatic annulus to hold in the palm before namely go up in working desk, prevent the) of electrostatic injury chip of human body, produce acuteness lightning as the cloud layer of charge instant puncture that stores in cloud layer, like can cleavaging the earth, and it is normally when wet comes, form electric conduction because air humidity is big easily to be connected.

 

 

So, how to prevent electrostatic discharge to injure? Change bad situation to decrease from fountainhead of course above all electrostatic (decrease to wear abb attrition, less for instance kind the) such as temperature and humidity of air of sweater, control, of course this is not the focal point that we debate today. How is protective circuit involved inside circuit when we should discuss today, have when the outside electrostatic when our electron yuan parts of an apparatus or system can ego protection avoids report of quiet and secluded to damage (install) of a lightning rod namely actually. This also is the number one difficult problem of design of a lot of IC and manufacturer, a lot of companies have the group that designs ESD technically, I tell a principle that explains ESD protection stage by stage and attention to nod from the basiccest theory with everybody today, the PN that you can tell before discovery writtens guarantee / canal of diode, dynatron, MOS, all used ……

 

When the special subject previously explains theory of PN knot diode, had told diode to have a character: guide is connected end reversely (the curricular) that does not remember break up, and slant instead voltage continues to increase can produce avalanche puncture (Avalanche Breakdown) and guide, we say for clamp diode (Clamp) . This is the theoretical foundation that we design electrostatic protection place to need, we use this to end reversely namely character lets this bypass be in when regular job disconnect condition, and the outside has electrostatic when this bypass diode produces avalanche puncture and formed bypass route to protect in-house circuit or grid (the cistern in similar home has an excessive water mouth, prevent faucet to forgot to close to bring about) of whole toilet flood. So the issue came, this puncture did this protection circuit die thoroughly? Be one-time? The answer is not of course. The puncture cent that PN writtens guarantee is planted, it is electric puncture and thermal breakdown respectively, what electric puncture points to is avalanche puncture (low density) with Qi Na puncture (high concentration) , and this report puncture basically is to carry flow child the electron with collision ionization new generation – hole is right (Electron-hole) , so it is recoverable. But thermal breakdown is not recoverable, because quantity of heat gathers,bring about silicon (Si) by melt burn down. So we need control to be in guide the instant that connect controls electric current, general meeting establishs ties again in protective diode a tall resistor, additional, is everybody OK does draw inferences about other cases from one instance understand why is the area of ESD cannot of Form Silicide? Still have everybody a theory, ESD is to be on the side of the Pad that chip input carries normally, cannot be inside chip, because we always are the electrostatic need of hope outside for a short while discharge dropt, be put inside to be able to have delay (attention before me anatomical has diode on the side of that chip PAD. Have those who put two class ESD even, achieve the goal of double protection.

 

 

Before the principle that says ESD and Process, we explain the standard of next ESD and test method first, according to electrostatic generation means and the scathing mode to circuit differ to divide normally test way for 4 kinds: Mode of human body discharge (HBM: Mode of discharge of Human-Body Model) , machine (Machine Model) , component charges mode (CDM: Mode of induction of Charge-Device Model) , electric field (FIM: Field-Induced Model) , but before industry is used normally two kinds of mode will check (HBM, MM) .

 

Mode of human body discharge (HBM)

 

It is human body attrition of course the charge that generated charge to come up against chip suddenly to release causes breakdown of chip burn down, the autumn and others lay a finger on often get an electric shock is this reason. Industry also has mark to the ESD standard of HBM but abide (MIL- STD-883C Method 3015.7, capacitance of equivalent human body is 100pF, resistor of equivalent human body is 1.5Kohm) , or standard of international electron industry (EIA/JESD22-A114-A) also has a regulation, see you want Follow which. If be MIL-STD-883C Method 3015.7, it sets those who be less than <2kV to be Class-1, in 2kV~4kV for Class-2, of 4kV~16kV for Class-3.

 

 

Machine discharge mode (MM)

 

It is a machine of course (if Robot) is mobile,by Pin the foot is released when the chip of electrostatic lay a finger on of generation, second standard is EIAJ-IC-121 Method 20(or standard EIA/JESD22-A115-A) , because,equivalent machine resistor is 0 (metallic) , capacitance is 100pF as before. Because the machine is a metal and resistor is 0, discharge time is very so short, it is Ms almost or between Us. But more serious problem is, it is as a result of equivalent resistor 0, electric current is very so big, so even if the harm that the MM discharge of 200V also discharges than the HBM of 2kV is great. And because machine itself has a lot of lead to be able to produce coupling effect each other, so electric current can change along with time and interference changes.

 

 

The GOI inside similar FAB checks the test method of ESD, he gives an ESD voltage first after appointing Pin, after lasting for some time, come back to check electric sex to look to whether damage again next, the ESD voltage that add a Step sure again lasts for some time again, measure electric sex again, till,relapse so puncture, the critical voltage that right now puncture voltage is ESD puncture (ESD Failure Threshold Voltage) . Normally we are to give circuit to hit voltage 3 times (3 Zaps) , to reduce test cycle, normally initiative voltage uses the 70% ESD Threshold of standard voltage, every Step can adjust 50V according to him need or 100V.

 

(1) . Stress Number = 3 Zaps. (5 Zaps, the Worst Case)

(2) . Stress Step 

ΔVESD = 50V(100V) For VZAP <=1000V

ΔVESD = 100V(250V, 500V) For VZAP>1000V

(3) . Starting VZAP = 70% Of Averaged ESD Failure Threshold (VESD)

 

Additional, because the Pin residue of every Chip is very much, you are each Pin test or assorted Pin test, so meeting cent is a few kinds of combination: I/O-pin checks (test of Input And Output Pins) , Pin-to-pin, Vdd-Vss test (the input carries output) , Analog-pin.

 

1.I/O Pins

 

Do ESD to check to Input-pin and Output-pin respectively namely, and charge has the cent that losing, have 4 kinds of combination so: Negative electric charge of positive electrical charge of Input+ positive electrical charge, Input+ negative electric charge, Output+ , Output+ . Check Input moment, criterion overall surplus of Output and other Pin is received (Floating) , vice versa.

 

 

2.pin-to-pin checks

 

Electrostatic discharge happens between Pin-to-pin to form loop, but if want often combination of two feet test is too much, because any it is certain after I/O gives voltage to if want to arise to whole circuit,be affected it is to pass VDD/Vss ability to be opposite first whole circuit power supply, so improved edition is added with some I/O-pin or negative ESD voltage, other and all I/O a ground connection, but input and output at the same time float is received (Floating) .

 

 

Between 3.Vdd-Vss electrostatic discharge

 

Electrostatic discharge happens between Pin-to-pin to form loop, but if want often combination of two feet test is too much, because any it is certain after I/O gives voltage to if want to arise to whole circuit,be affected it is to pass VDD/Vss ability to be opposite first whole circuit power supply, so improved edition is added with some I/O-pin or negative ESD voltage, other and all I/O a ground connection, but input and output at the same time float is received (Floating) .

 

 

4.Analog-pin discharge checks

 

Because imitate circuit is very much poor cent is compared right (Differential Pair) or operation amplifier (OP AMP) is to two inputs are carried, prevent an attaint to bring about poor cent to compare right or operation invalidation, so need does ESD test alone, be aimed at these two Pin only namely of course, other Pin overall surplus is received (Floating) .

 

 

Good, the principle of ESD and test part tell here, the Factor that Process and design tell to go up then below as rub of Er law narrow further, size of parts of an apparatus is smaller and smaller, the ties is close more and more shallow, GOX is thinner and thinner, electrostatic puncture is so easier and easier, and Cheng Li range is made in Advance, silicide introduces also can let electrostatic puncture become more acerb, so almost all chip designs should overcome electrostatic puncture problem.

 

The Process that electrostatic discharge protection can carry from FAB is solved, the Layout that also can design end from IC will design, so you can see Prcess has the Option Layer of an ESD, the design regulation that there perhaps is ESD inside Design Rule can choose to wait a moment for the client. Of course some of client also meets him to design ESD according to the electric sex of SPICE Model through Layout.

 

1, the ESD that makes Cheng go up

 

Or changes PN form, or changes the laden resistor that PN writtens guarantee, and change PN knot can rely on ESD_IMP only, and change and the laden resistor that PN writtens guarantee, perhaps establish ties with Non-silicide namely the method of resistor.

 

1) the ESD Implant of Source/Drain

 

Because our LDD structure forms two shallow ties very easily in Gate Poly both sides, and the pointed horn electric field of this simple written guarantee compares concentration, and because be simple written guarantee, it and Gate are so closer, the effect of extreme electric field that suffers Gate so is bigger, so such LDD pointed horn is in be able to bear or endure the ability that ESD discharges is poorer (<1kv) , if such Device is used,be in so I Esd= "" >4kV) . But such word the Gate of this additional MOS must very long prevent break-through (Punchthrough) , and because parts of an apparatus is different, so need extracts the SPICE Model of parts of an apparatus alone.

 

9

 

2) contact aperture (the ESD Implant of Contact)

 

The N+ in LDD parts of an apparatus hits the boron of a P+ below the aperture of leakage pole, and deepness should exceed N+ to leak extremely (the deepness of Drain) , the puncture voltage drop that can let original Drain so is small (8V- – > 6V) , can guide from Drain puncture first before LDD pointed horn produces puncture so the puncture that protects Drain and Gate thereby. So such design can maintain measure of parts of an apparatus changeless, and MOS structure does not have a change, reason does not need to extract SPICE Model afresh. Of course this kind of intelligence is used at Non-silicide to make Cheng, otherwise you also hit Contact not to go in Implant.

 

3) SAB (SAlicide Block)

 

General us to reduce MOS interrelate capacitance, we can use Silicide/SAlicide to make Cheng, but if such parts of an apparatus work to be carried in output, resistor of our load of parts of an apparatus becomes low, outside ESD voltage will very easy between LDD and Gate structure puncture injures full to load, in the Silicide/Salicide of the MOS that outputs class so we connect regular meeting to use cover of SAB(SAlicide Block) light to hold off RPO, do not form Silicide, increase cost of a Photo Layer, but ESD voltage can raise 4kV from 1kV.

 

4) standard of series connection resistance

 

This kind of method need not raise smooth hood, should be most of be economical, the principle is a bit similar the 3rd kind (SAB) raises resistance standard, I give his series connection intentionally a resistor (for instance Rs_NW, or HiR, wait for) , also obtained the means of SAB so.

  

2, the ESD on the design

 

This leans the architect’s time completely, some companies had been carried in design regulation offer Solution giving a customer, the client wanted to go according to the picture only, the can rely on him client only Designer that does not have a little, regulation of a lot of designs is to be being written this is Guideline/reference only, not be Guarantee.

 

It is a Gate/Source/Bulk commonly short receive together, bear Drain knot in I/O end the surge of ESD (Surge) voltage, NMOS says it is GDPMOS (Gate-to-Drain PMOS) for what GGNMOS (Gate-Grounded NMOS)PMOS says. It is with NMOS exemple, the principle is Gate closes position, the PN knot of Source/Bulk is short originally receive 0 those who slant, when I/O end has big voltage, criterion puncture of avalanche of Drain/Bulk PN knot, instantaneous Bulk has big electric current and underlay resistor to form the PN that presses difference to bring about Bulk/Source to slanting, so transverse NPN canal enters the parasitism of this MOS enlarge area (emissive knot is slanting, market report knot slants instead) , present character so, rise to protect action. PMOS is the same as manage derivation.

 

 

This principle looks simple, but the marrow of the design (what is Know-how) ? How to spark BJT? How to maintain? How to maintain HBM>2KV Or 4KV?

 

How to spark? Must have enough big underlay electric current, what so development arrived to be used generally now later is much show across is shunt-wound structure (Multi-finger) . But this kind of structure is main technical issue is base area width increases, magnify coefficient is reduced, not allow so Yi Kaiqi. And as Finger measure increase, can bring about the even open between every Finger to become very difficult, this also is the bottleneck place that ESD designs.

 

 

If want to change this kind of problem, have two kinds of ways probably (because of Triger is voltage, improving voltage or is resistor or it is voltaic) : 1, the Non-Silicide area that uses SAB(SAlicide-Block) to form a tall block on the Drain of I/O, make resistor of leakage pole diamonds increases, and make ESD electric current distributings evener, increase release capacity thereby; 2, increase a P-ESD (Inner-Pickup Imp, similar the osculatory aperture P+ ESD Imp) above, a P+ is hit below N+Drain, reduce the avalanche puncture tension of Drain, have more avalanche puncture electricity earlier (detailed sees document thesis: Inner Pickup On ESD Of Multi-finger NMOS.pdf) .

 

To ESD has two little common sense to want to share with everybody:

 

We can see 1)NMOS normally better character, but actually PMOS has character very hard, and PMOS is able to bear or endure it is good that the character of ESD compares NMOS generally, this truth is the same as HCI effect, because of generation of NMOS puncture moment is an electron,basically be, mobility is very big, isub is very so big make easily Bulk/Source guide is connected, but PMOS is difficult cough up.

 

2) Trigger voltage / Hold voltage: Trigger voltage is of course before will the first inflection point (Knee-point) , the puncture voltage of parasitism BJT, and should upright between BVCEO and BVCBO. And Hold voltage should be maintained namely continuously ON, but cannot enter bar to lock up again (Latch-up) condition, enter puncture 2 times otherwise (thermal breakdown) and damaged. Still having an idea is puncture electric current 2, after entering Latch-up namely, I^2*R quantity of heat is added suddenly bring about silicon to melt, and this wants current limliting namely, can pass control W/L, perhaps increase tall block of a current limliting, the simplest the most commonly used method is the distance that pulls big Drain / the distance that pulls big SAB (the common practice) of ESD Rule.

 

3, grid coupling (Gate-Couple) ESD technology

 

We just had been told, the bottleneck that the ESD of Multi-finger designs is the uniformity of open, have 10 Finger suppose, and when ESD discharge happens, these 10 Finger are not met certainly guide at the same time (it is commonly guide because of Breakdown a) , often see only 2-3 raises Finger meeting forerunner is connected, because cannot make the relative position of every Finger reachs the way that draw a line on layout,this is identical be caused by, this 2~3 raises Finger to guide, ESD electric current sheds the Finger that raises to this 2~3 centrally, and the Finger of other still is to maintain shut, so its ESD defends ability equivalent defends at what only 2~3 raises Finger ability, and rather than of 10 Finger defend ability. This namely why package dimension has been done very greatly, but ESD defends ability was not like the main reason that anticipates kind of ground to rise, add dozen of area to fail to anticipate bring ESD to increase, how to do? Actually very simple, want to reduce Vt1(Trigger voltage) namely, we raise the kind of voltage through grid, let underlay open replaces puncture and carry bellwether to connect generation underlay electric current first, can let other Finger also leave together at that time open enter on-state, let every Finger bear ESD electric current, produce the ESD effect of large area truly.

 

Finger also leaves together open enter on-state, let every Finger bear ESD electric current, produce the ESD effect of large area truly.

 

But the ESD design of this kind of GCNMOS has a drawback is raceway groove open produced electric current to cause bar oxygen breakdown easily, what so he disappears is a kind of very good ESD design program, and the impact that active area is smaller bar controls is bigger, and active area is larger more difficult open, hold very hard so.

 

4. still has a kind of complex ESD to protect circuit: Brake of brilliant of silicon controlled rectifier is in charge of (SCR: Silicon Controlled Rectifier  

 

(SCR: Silicon Controlled Rectifier) 

 

The PNPN structure of the CMOS parasitism that it has told before us namely sparks arise and Latch-up, realize the protection to circuit through ON/OFF, everybody can review, as long as on one inside those Factor think of a way that control LATCH-up make its happen OK, can apply to Layout only nevertheless, cannot apply to Process, otherwise Latch-up wants Fail again.

 

Finally, the design knowledge of ESD is too intimate, be cast a brick to attract jade-offer a few commonplace remarks by way of introduction so that others may come up with valuable opinions gives everybody popular science only here, basically is the plan of ESD like below a few kinds of: ? A few kinds of methods such as BJT of OS of  of Peng of  of  of ⒍ of a low bank of earth between fields of Qian crack handleless cup, parasitism, SCR(PNPN Structure) . And ESD is mixed not only Design is relevant, more the Process with FAB is relevant, and knowledge is too intimate, I also am not to understand very much here, cannot give again everybody is thorough. Of course art line of business specializes in knowledge is infinite, ability learns to be able to be achieved ceaselessly only in the job close more cost-effective.