To the installation of capacitance, what should mention above all is installation distance. The look is worth the smallest electric capacity, have highest syntonic frequency, go Ou radius is the smallest, because this is put in most the position that stands by chip. Look value is some more largish can be apart from a bit far, the outerest place a look to be worth the biggest. But, all is opposite this chip goes the capacitance of Ou stands by chip as far as possible.

 

The graph is a case that puts the position below. The capacitance grade in this exemple follows concern of 10 times grade roughly.

 

 

Still a bit want to notice, when place, had better distributing equably in chip all around, to each the grade that hold a cost wants such. Normally chip is in what when designing, considered power source and ground cite a base to arrange the place, distributing to go up in 4 edges of chip equably commonly. Accordingly, voltage disturbs in chip all around exist, go Ou also must go equably to area of whole chip place Ou. If go up the upside that the 680pF capacitance in the graph puts in chip, because existence goes Ou radius problem, cannot be opposite so chip is lower voltage disturbs to go very well Ou.

 

 

When installing capacitance, should from solder dish draw a paragraph of small derivative line, had passed aperture and join of power source plane next, ground connection end also is same. Shed the voltaic loop of classics capacitance to be so: Power source is planar – ” cross aperture – ” derivative line – ” solder dish – ” capacitance – ” solder dish – ” derivative line – ” cross aperture – ” ground level, graph 2 intuitionistic indication circumfluence method of electric current.

 

 

The first kind of method from solder dish derivative very long derivative line has joined next aperture, this meeting introduces very big parasitism inductance, must avoid such doing, this is the worst installation means.

 

The 2nd kind of method is in solder dish two end points are proximate solder dish stiletto, smaller than area of road of the first kind of method much, parasitism inductance is lesser also, can accept.

 

The 3rd kind is in solder dish flank stiletto, reduced loop area further, parasitism inductance is smaller than the 2nd kind, it is better method.

 

The 4th kind is in solder dish two side stiletto, compare with photograph of the 3rd kind of method, be equivalent to capacitance each end is to had passed the paralell connection of aperture to accept power source plane and ground level, smaller than inductance of the 3rd kind of parasitism, want a space to allow only, use this kind of method as far as possible.

 

Last kinds of method is in solder dish on direct stiletto, parasitism inductance is the smallest, but soldering is to may appear problem, whether to use should see process capability and way. Recommend use the 3rd kind to mix the 4th kind of method.

 

Need emphasizes a bit: Some engineers to save a space, let many capacitance use sometimes communal cross aperture, any circumstances fall to be not done so. Had better think method optimizes the design that capacitance combines, reduce capacitance amount.

 

 

Because print a line wider, inductance is smaller, from solder dish to the derivative line that crosses aperture as far as possible broaden, if likelihood, mix as far as possible solder dish width is identical. Such even if 0402 enclosed capacitance, you also can use the derivative line with broad 20mil. Derivative line and institute of plan of as above of installation crossing aperture are shown, note all sorts of size in the graph.