Bypass capacitance is a power source the communicates heft interference in perhaps inputting signal divides a target as filter.

 

 

Had bypass electric capacity, the communication in power source 5V heft —— wave motion undertakes filter is divided. Turn blue weaveform into pink weaveform. Generally speaking, stand by power source to place.

 

Go the power source pin that Ou capacitance is chip, because oneself uses the signal in electric process to jump,change the power source pin of generation external undee output, we undertake with capacitance filter is divided.

 

pin of signal power source, output interference divides a target as filter, prevent to disturb signal to return power source.

 

 

The formation of aiguille electric current:

 

The size of the voltaic Ioh that when digital circuit outputs tall n, pulls from power source and the voltaic Iol that the fill when low n is outputted enters is different commonly, namely: Iol ＞ Ioh. The TTL of the following graph and blame door are the formation of a demonstrative aiguille electric current:

 

 

Output voltage is like right graph (A) be shown, the weaveform of theoretic source current is like right graph (B) , and practical source current is sure to be like right graph (C) . By the graph (C) can see the source current when tall n is being changed by low n in output has an aiguille with brief and very big range. The type that the weaveform of aiguille source current uses parts of an apparatus along with place and the capacitance that output end receives are laden and different.

 

The main reason that produces aiguille electricity is:

 

Guide at the same time inside short design of canal of the T3 that outputs class, T4. In the process that turns to tall n by output low n with blame door, those who input voltage is negative jump change to produce very big retrorse drive electricity inside the base loop of T2 and T3, because the saturated deepness of T3 is designed more greatly than T2, retrorse drive electric current will make T2 is broken away from above all saturated and end. After T2 ends, its collector potential rises, make T4 guides. But right now T3 has not broken away from saturation, because this is in extremely so short that the T3 inside the design and T4 will guide at the same time, produce very big Ic4 thereby, make source current forms aiguille electric current. The R4 in the graph is designed to restrict this aiguille electric current just about.

 

This should be their substaintial distinction. Go Ou capacitance is equivalent to batteries, avoid to make voltage drops as a result of voltaic mutation, be equivalent to filter ripple. Specific look value is OK the size according to electric current, ripple size of expectation, bulk of effect time will calculate. Go Ou capacitance is general very big, right more high-frequency noise, disable basically. Bypass capacitance is aimed at namely high frequency come, the frequency impedance that used electric capacity namely is characteristic. Just bypass capacitance is bypass of finger height frequency commonly, raise discharge of a low impedance to defend an approach to high frequency switch noise namely. Capacitance of high frequency bypass is compared commonly small, the basis is syntonic frequency is 0.1u commonly, 0.01u, and go coupling capacitance is compared commonly big, it is 10u bigger perhaps, parameter distributings in basis circuit, and the metabolic bulk of drive electric current will decide.

 

Bypass capacitance

 

Bypass capacitance (Bypass) it is a high frequency noise in inputting signal divide a target as filter, before the filter of high frequency clutter that class carries is divided.

 

The main function of bypass capacitance is to produce shunt of a communication, thereby those does not need energy that expunction enters easy feeling area. Bypass capacitance reduces the demand of transient state electricity of pair of power source module commonly as parts of an apparatus of high frequency bypass. Normally aluminium electroanalysises capacitance and tantalum capacitance suit bypass capacitance quite, its capacitance value depends on the demand of transient state electricity on PCB board, be in commonly 10 to 470µF limits inside.

 

Go Ou capacitance

 

Go Ou capacitance (Decoupling) also say to retreat Ou capacitance, the interference of the output of the power source foot that is a chip divides a target as filter. Go Ou capacitance mixes in integrated circuit power source between the ground have two effect: The harbour that is this integrated circuit on one hand can capacitance, the high frequency noise that on the other hand bypass drops this parts of an apparatus (electric capacity is small to high frequency impedance, will have diarrhoea comes GND) .

 

In digital circuit, from a condition when circuit changeover is another kind of condition when, can produce a very big aiguille electricity on power supply cord, form transient noise voltage, the regular job of the class before meeting influence. This is coupling. The memory such as the parts of an apparatus with big change of the weak to noise ability, electric current when closing and ROM, RAM parts of an apparatus, should be in the power supply cord of chip (Vcc) with ground wire (GND) receive directly go Ou capacitance.

 

Be worth typically in digital circuit is 0.1µF. The typical cost of the distributinging inductance of this capacitance is 5µH. Of 0.1µF go to what Ou capacitance has 5µH distributinging inductance, its collateral resonance frequency is controlled in 7MHz about, that is to say, it is better to have to the noise under 10MHz go Ou effect, act well scarcely to the noise of 40MHz above. The capacitance of 1µF, 10µF, collateral resonance frequency is in 20MHz above, the effect of high frequency noise wants purify better. 10 every or so integrated circuit should add to fill discharge electric capacity, or a harbour can capacitance, optional 10µF is controlled. Had better not use electroanalysis capacitance, electroanalysis two film coil capacitance, this kind of structure that coils is in high frequency when expression is inductance. Want to use tantalum capacitance or polycarbonate electric capacity. Go of Ou capacitance choose lax case, can press C=1/F, namely 10MHz takes 0.1µF, 100MHz takes 0.01µ .

 

Case analysis:

 

Use go Ou and do not use go the amortize circuit of Ou (measure an outcome)

 

 

To take Ou capacitor is mixed do not take Ou capacitor (C1 and C2) the amortize circuit that is used at drive R-C load below the circumstance. We notice, using go below the circumstance of Ou capacitor, the output signal of circuit is included high frequency (3.8MHz) oscillation. To going the amplifier of Ou capacitor, normally low, transient state answers meeting occurrence stability poor, start occurrence breakdown and other a variety of unusual problems.

 

Carry coupling and the electricity that do not carry coupling circumstance to fall

 

 

The inductance of mark of power supply cord will restrict transient electric current. Go Ou capacitance and parts of an apparatus are very adjacent, the inductance of voltaic method is very accordingly small. In transient process, this capacitor can be in parts of an apparatus offers very short time introversion exceed many electric current. Did not use go the parts of an apparatus of Ou capacitance cannot provide transient electricity, the in-house node of amplifier will be accordingly flagging (call interference normally) . Without go its interior electrical interference can bring about the parts of an apparatus of Ou capacitance job of parts of an apparatus is discontinuous, the reason is in-house node was not obtained slant correctly buy.

 

Good with bad PCB the contrast of board side position

 

Besides use go outside Ou capacitor, accepting shorter low impedance connection even. Will good go position of coupling board side and bad position undertook contrast. Should try to let go from beginning to end the distance that coupling join maintains shorter, avoid to appearing at the same time via, the reason is via can increase inductance. The manual meets major product to go out of coupling capacitor recommend a value. If did not give out, can use 0.1uF.

 

 

Ou capacitance goes putting when PCB layout

 

To the installation of capacitance, what should mention above all is installation distance. The look is worth the smallest electric capacity, have highest syntonic frequency, go Ou radius is the smallest, because this is put in most the position that stands by chip. Look value is some more largish can be apart from a bit far, the outerest place a look to be worth the biggest. But, all is opposite this chip goes the capacitance of Ou stands by chip as far as possible.

 

The graph below the 1 case that puts the position namely. The capacitance grade in this exemple follows concern of 10 times grade roughly.

 

 

Still a bit want to notice, when place, had better distributing equably in chip all around, to each the grade that hold a cost wants such. Normally chip is in what when designing, considered power source and ground cite a base to arrange the place, distributing to go up in 4 edges of chip equably commonly. Accordingly, voltage disturbs in chip all around exist, go Ou also must go equably to area of whole chip place Ou. If go up the upside that the 680pF capacitance in the graph puts in chip, because existence goes Ou radius problem, cannot be opposite so chip is lower voltage disturbs to go very well Ou.

 

The installation of capacitance

 

When installing capacitance, should from solder dish draw a paragraph of small derivative line, had passed aperture and join of power source plane next, ground connection end also is same. Shed the voltaic loop of classics capacitance to be so: Power source is planar – > cross aperture – > derivative line – > solder dish – > capacitance – > solder dish – > derivative line – > cross aperture – > ground level, graph 2 intuitionistic indication circumfluence method of electric current.

 

 

The first kind of method from solder dish derivative very long derivative line has joined next aperture, this meeting introduces very big parasitism inductance, must avoid such doing, this is the worst installation means.

 

The 2nd kind of method is in solder dish two end points are proximate solder dish stiletto, smaller than area of road of the first kind of method much, parasitism inductance is lesser also, can accept.

 

The 3rd kind is in solder dish flank stiletto, reduced loop area further, parasitism inductance is smaller than the 2nd kind, it is better method.

 

The 4th kind is in solder dish two side stiletto, compare with photograph of the 3rd kind of method, be equivalent to capacitance each end is to had passed the paralell connection of aperture to accept power source plane and ground level, smaller than inductance of the 3rd kind of parasitism, want a space to allow only, use this kind of method as far as possible.

 

Last kinds of method is in solder dish on direct stiletto, parasitism inductance is the smallest, but soldering is to may appear problem, whether to use should see process capability and way.

 

Recommend use the 3rd kind to mix the 4th kind of method.

 

Need emphasizes a bit: Some engineers to save a space, let many capacitance use sometimes communal cross aperture, any circumstances fall to be not done so. Had better think method optimizes the design that capacitance combines, reduce capacitance amount.

 

Because print a line wider, inductance is smaller, from solder dish to the derivative line that crosses aperture as far as possible broaden, if likelihood, mix as far as possible solder dish width is identical. Such even if 0402 enclosed capacitance, you also can use the derivative line with broad 20mil. If the graph is shown 4 times,derivative line and Guo Kongan are installed, note all sorts of size in the graph.