Has been the area spreading copper between SW and inductance jumped over greatly more?

Has been the area spreading copper between SW and inductance jumped over greatly more?

[introduction]Switch power source is the electric energy transformer that is core with power MOS, the parameter besides chip oneself can produce bigger effect to electric energy quality outside, the design of PCB also is very important.

Switch power source is the electric energy transformer that is core with power MOS, the parameter besides chip oneself can produce bigger effect to electric energy quality outside, the design of PCB also is very important.

Today, we will are with simple Buck circuit exemple, set out from different point of view, share the result of a few designs that spreads copper about switch side PCB with everybody.

Above all, switch side, namely the SW that we often say, it is the very crucial position in Buck circuit, it is input loop and the node that output loop, also be the place that MOS of bridge arm power is linked together directly at the same time.

Has been the area spreading copper between SW and inductance jumped over greatly more?

Generally speaking, with the signal that power MOS is linked together, the area spreading copper of PCB should be designed a few more greatly as far as possible, basically be two respects think:

It is the electricity that power loop need takes bigger on one hand, on same space, increase those who spread cupreous width to be able to increase a line to connect shed ability, reduce method loss.

Has been the area spreading copper between SW and inductance jumped over greatly more?

On the other hand, spread copper with what power MOS is linked together directly, also assuming parts of an apparatus to come loose hot part. We know, medicinal powder the bottleneck that heat energy force often can become power source chip to output ability. Because the thermal conductivity of chip Pin foot is better, chip kernel often can be less than the thermal resistance that encloses the surface to the thermal resistance of PCB, this also means chip to be heated up for the most part is to pass chip Pin foot to guide of the dissipation after PCB, that raises the area spreading copper of SW, to Buck chip medicinal powder heat energy force, also can have the promotion of certain level.

Has been the area spreading copper between SW and inductance jumped over greatly more?

But, whether do this spread copper to had been jumped over greatly more with respect to what mean SW?

The answer is negative.

If be spent from noise dimension,go looking, SW is carrying on the input loop that Buck develop attacks and output loop, as the switch switch of MOS, the tension that SW handles also can produce periodic pulse change. In the meantime, the electric current of SW also the high frequency switch as MOS, present the wave motion of regularity.

When SW the area that spread copper greatens, also can increase subsequently to the parasitism capacitance of referenced ground so, the noise that wave motion of high frequency voltage brings reachs referenced ground more easily through parasitism capacitance coupling, affect the identifying of other sampling signal thereby.

Has been the area spreading copper between SW and inductance jumped over greatly more?

In the meantime, metabolic electric current can produce metabolic magnetic field in the space, cross when magnetism lead close when coil, meet the induction gives voltage noise, produce certain effect to the signal around. As the addition of the area that spread copper, the radiation range of interference is wider also.

Has been the area spreading copper between SW and inductance jumped over greatly more?

So, to reduce the effect of pair of circumjacent signal as far as possible, we hope the Yue Xiaoyue of the area that spread copper of SW is good.

Additional, we also do not suggest to had dug hole in SW place.

In applying actually, to reduce the effect of power source noise to signal catenary, we can add a complete GND to regard noise screen as the layer below power source layer. Once SW place had increased opening, broken annulus the integrality of screen layer, noise can arrive along interference crossing aperture the signal of other layer is transmitted.

Has been the area spreading copper between SW and inductance jumped over greatly more?

So, how to resolve afore-mentioned contradiction?

The width spreading copper of SW needs to make sure cross section has enough electricity to connect shed ability, this is first requirement. Generally speaking, the PCB with 1OZ thick copper, design of width taking a line is compared in 15mil/A left and right sides reasonable. On this foundation, shorten as far as possible SW arrives the distance between inductance, will reduce the interference of pair of circumjacent signal.

Has been the area spreading copper between SW and inductance jumped over greatly more?

We can spread copper and the area that input shop copper through increasing GND of power source chip, come to those who promote MOS come loose heat energy force. What dissolve this design ably to go up so is bit more contradictory.

Article origin: System of MPS core source

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