Can effect becomes a key in semiconductor industry

 

Insert wall OK and simply when the system in order to receive electric power when, the power comsumption that complex chip produces is not real problem. The mainest function is primitive function, express with GHz or MIPS. However, as after was being reached 2000, use of wireless and mobile equipment in great quantities, this index tends produce change. To the equipment of batteries power supply, twice batteries charges the time between almost as important like the MIPS n of the smartphone.

 

Now, let our drop back one pace, semiconductor (with the electron) the source that the industry counts power comsumption, include a server, memory, tall powermeter calculates (HPC) , wired network, 4G is mixed 5G radical stands, these application need high-powered. Semiconductor guild (SIA) study a company with semiconductor (SRC) “ released to restart 2015 IT revolution: The action rises ” report, include to lay a plan among them:

 

Graph 1: Calculative total specific power consumption (origin: SIA)

 

Apparent, data center is large family of specific power consumption, other application specific power consumption (like car and content couplet net) also be in promotion, IC of net of most content couplet is to be in margin system. In fact, industry has been accepted now computational ability (CPU or DSP) the demand that brings into margin system, because be pushed up,send data (to content couplet net advocate station) and transmit data downward (once processing is over data) apparent either right choice. And to driving automatically the system such as the car, can appear not acceptability defer:

 

In the article, a variety of application of the IC that we will discuss to be developed on mature technology node (with the most advanced node, be like 14/16 Nm, 10 Nm or correspondence of 7 Nm photograph) , in content couplet net, car, consuming the likelihood such as the electron is likely also not be batteries power supply. The target of our set is: Reduce IC power comsumption, hold property at the same time, cut development time and cost, use identical IC, need not power source government works, identify potential problem (noise tolerance, string together faze to wait) . The solution that the article offers can achieve this one goal, to TTM, cost and correct function do not have any influences.

 

Graph 2: Use medium power source issue

 

Reduce all sorts of solutions of SoC power comsumption

 

As above, since 2000, wireless and mobile industry is the pioneer of technique of power source management all the time. The design group of SoC of responsible application processor (the OMAP that is like TI, it is to be connected high next, samSung, the apple) had implemented strategy of power source government on systematic level mobile phone. Technology of power source management is very sophisticated, so that they realize function of interiorly report source control very quickly (IC of power source management or PMIC) over need exterior parts of an apparatus. All sorts of solutions here will be carried out in SoC interior, do not need PMIC, because the target is,maintain cost and before use PMIC identical or lower level.

 

It is OK to review here all sorts of technologies that reduce SoC power comsumption.

 

Power source region manages

 

Before implementing any specific power network IP or distribution strategy, want to consider to define power source region above all. Remember please, power source region the basis the function in SoC piece have a definition. A functional piece can involve the unit of different type, for example CPU and digital level unit piece, they are linked with SRAM memory together. These module can fall to achieve electric energy from different power source in different voltage.

 

Defined all sorts of region, the target is to realize the specific power of specific power region to allocate, found power island. Every region can be kept apart with the others of SoC and cut off the power (or electrify) , and won’t affect region of other power source. We will see at the back of the article how deploy this report source control is politic.

 

Dynamic voltage frequency adjusts (DVFS)

 

Dynamic power comsumption expresses by the following formula:

 

 

Here:

 

 

The combination of power source voltage and frequency has stereo effect to total power comsumption, 2 dependence that have pair of voltage because of dynamic power comsumption and the linear dependence to frequency. The solution can drop intelligent division report working frequency, reduce power source tension at the same time.

 

Main idea is to be in give frequency to fall to reduce power source tension as far as possible, still maintain the correct operation of certain function at the same time. Voltage can drop only a certain critical level, exceed this level to be able to appear time breakdown.

 

When using method of every function DVFS, already defined every function power source suppose / clock region carried out add circuit, power comsumption of SoC overall situation can be reduced apparently, identical or it is better to hold property at the same time, the function that so that become,the need when other function maintains mourn in silence uses can move normally (namely: Reduce tension) .

 

Notebook computer, server and mobile equipment use dynamic voltage and frequency extensively to adjust (DVFS) come managing the sources of energy, and DVFS is in other applying (car, consume an electron. . . . . . ) inchoate phase still is in start level. According to experimental result, DVFS has the energy-saving latent capacity that showing. DVFS just controls one of a few kinds of methods of power comsumption of CMOS circuit trends. We must remember, its use meeting brings a series of test and verify and implementation challenge, but the aspect of SoC power comsumption that DVFS is reducing dynamic mode to fall is very significant.

 

Graph 3: Specific power consumption (trends and leakage of electricity) the relation with voltage

 

Be close to threshold value voltage

 

General power is static state or leak power and dynamic power is total close. As voltage of threshold value of voltage front transistor (Vt) drop, switch power is reduced but at the same time leakage current increases. This is meant must find the optimal combination between leak and switch power source, if pursue,3 are shown.

 

Be close to threshold value voltage (NTV) will choose inside the voltage range that offers the smallest energy (refer to a graph 3) , hold functional region job at the same time. NTV is technique of a kind of outstanding power source management, in can effect (EE) the respect gave out first-rate result, if pursue,4 are shown. These results come from the measurement to Intel Pentium, we can notice, 0.45 V (approach threshold value) ) , EE achieves every tile 5830 Mips, with rated voltage (1.2 V) the EE that is 1240 Mips / Watt undertakes comparative. The first defect can see in same figure: Be in nominal voltage (1.2 V) below, chip frequency achieves 915 MHz, and in NTV (0.45 V) when, it has 60 MHz only.

 

NTV can provide outstanding result (power comsumption and can effect) , be in especially Morpheus or spark below mode, because SoC need not be below this kind of mode,run whole performance, for example brim of content couplet net is calculated or forever online sensor.

 

Graph 4: Can effect and functional voltage

 

Other technology: Body slants buy, GALS, . . . . . .

 

GALS technology is used at region of the biggest clock to manage efficiency. Should use one-way double synchronous device (like FIFO) example is changed cross clock border, realize optimal defer below the situation that does not need handclasp thereby. Can along interrelate the bell is attrib border when any link inside differentiate, and can bypass GALS component has synchronous operation.

 

Power source and voltage region are separated by electric separator, and should be used disconnect the technology shuts each functions piece. When power source region is shut, specific function piece when must holding position, should insert reservation register.

 

Anyhow, GALS is a kind efficient but very slashing (in project level) method of power source management, it involves specific design knowledge and the skill that use existing EDA tool. Accordingly, in implement other technology (if clock door accuses, government of power source region or DVFS) hind, should consider GALS.

 

Body slants buy is technique of a kind of chip management, the underlay bias voltage that can bring to bear on to the voltage of chip active part according to bringing to bear on will reduce power comsumption or improve performance. Although theoretic can bring to bear on to any underlay voltage, include volume, but body slants buy basically is used at the silicon on dielectric (SOI) brilliant is round. Completely extinct SOI (FD-SOI) the technology had caused attention of a few years, a few acting factories (SamSung, globalFoundries) with IDM (meaning law semiconductor) offerring 28 Nm, the ASIC function of 22 Nm and 14 Nm. The ASIC that is aimed at FDPower SOI technology is designed and do not compare bulk certainly more complex, but ecosystem is devoting oneself to to offer EDA tool and IP support system to slant at present buy.

 

Affect all sorts of power source issues of SoC integrality

 

To satisfy radical power budget target, design group may have no alternative, can move with extremely low power only, its are affected directly was to add crucial signal to electromagnetism (EM) the sensitivity of the effect that string together faze.

 

Because SoC of low power comsumption is had small much noise tolerance, accordingly, switch activity may bring about power source to transmit a network (PDN) ringing produces adverse effect to chip function.

 

In today’s design, clock and distribution network are the main contributor of integrated circuit breakdown, shake for example, clock deflection, electromigration, coupling noise and power distributing drop. Accordingly, function and risk avoid depend on clock and the dovish sex that distribution network designs, make of induction and magnetism effect build a model accurately to make main demand.

 

For example, one gives the distribution of digital module power supply the network, this number module has tall electricity demand and very fast switch activity (namely, peak value of tall electric current is absorbed in very swift transient state) . Such activity will cause distribution network (PDN) the ringing that go up, its and inductance (L) the rate with switch activity (Di / Dt) into scale. As the addition of switch activity, pass the coupling with PDN, the extent of ringing will increase, and the noise level on key or sensitive high frequency or very sensitive imitate signal. Another challenge is the low frequency noise that produces during mode is changed, this may produce functional problem.

 

Power includes dynamic power and leakage electric power. Dynamic power depends on total laden electric capacity, power source voltage and working frequency. Reduce any these parameter can bring about dynamic power comsumption reduce. But method of a kind of of PDN common design is to insert enough scale down to come the aiguille on screen pack sth resembling a net, because switch noise can bring about clock brim,appear aiguille of big electric current. The NMOS of CMOS grid is mixed during the rise that should input signal and decay time PMOS passageway guides at the same time when connecting, power of leakage of electricity is caused by the voltaic method between power source and ground.

 

Won’t get to ensure your SoC is designed power source or clock are relevant the influence of the problem, the technology that you must offer from seasoned engineer is benefited in support. Like imitate design, do not have any to be able to replace experience.

 

In the client’s SoC use power source manages IP

 

Region of implementation power source identifies

 

We need to define framework of SoC power source above all, because this is planted,the framework can change along with functional framework. This will be the first job of all sorts of functions that design personnel identifying to belong to region of same power source. This power region is not simple define by voltage, however with in give what the one part that makes same job anticipates below power mode all sorts of piece the function is relevant.

 

Had defined framework of this kind of power suppose, soC is differentiated to be N now region (N is inside 5 wider even range) . Can supply in the light of voltage (Vdd1 comes VddN) independent ground monitoring these inside the country each, and the architect can realize power allocation and power activity control in SoC class, below this kind of circumstance, use at the independent electrified wire netting of every Vddn. In this phase, dolphin Integration can be offerred by seasoned SoC Architectural Experts (SAE) the technical support that the engineer provides. These engineers are not simple FAE, they return source control of interiorly government report to carry out, interiorly is a client through us (the design serves) the SoC of development. Its power source manages IP to support region of 128 power source at most.

 

Graph 5: The power source region in SoC

 

Power source door accuses, control and allocate

 

Below the help of expert engineer, design group had defined all sorts of power source region, now is framework of power source of moment definition SoC, realize power source and clock to allocate in chip. Should be power supply of region of every power source, insert power source door to accuse in order to dominate this region. The door of patent power source of power source island that passes development controls device (the name is CLICK) , and voltage region interface (VDIC) , the expert is in help group all sorts of voltage regulator (LDO and DC-DC) in the plan with right choice, it is its organization the silicon IP library that configures beforehand.

 

We return those who put forward a support to be as high as 5.5 V to press protective module too. Offer clock to be this region, the client exceeds benefit from benefit from IP of clock of low power comsumption (the name is Gamma) . Use correct clock and distribution device crucial, because “ clock and distribution network are the main contributor of mechanism of integrated circuit breakdown, if shake, clock deflection, electromigration, coupling noise and power distributing drop ” , as above!

 

Graph 6: Power source door accuses, control and allocate

 

Chip class SoC designs personnel to will choose to control mains switch, VREG or body slant buy generator and clock, all parts of port of IP of power source network, for SoC kernel power supply. Because use modular IP solution (the name is MAESTRO) , implementation of pilot of mode of SoC power source is very simple. These unit are the module of elaborate design, compositive inside buy conflict governs a function, breakdown appears in can preventing SoC operation and transition.

 

If SoC design is used at voltage of this machine threshold value (NTV) or DVFS operation, combination of product of compositive IP issues a design to support to have this machine NTV and DVFS in Morpheus or working mode, if pursue,6 are shown.

 

Through abiding by the structure is mixed assemble regulation (name for DELTA regulation) , the complete power source that ensured we are compositive manages the consistency of IP product. The interior of the VREG that SoC design personnel can use themselves through adopting similar regulation develops implementation not to have seamed SoC compositive.

 

IP of management of compositive power source allows to offer On-SoC power source is transmitted and power source mode is controlled, main goal is the IP that offers all sorts of expert course and technical support, in order to come true energy-saving (EE) of SoC most safety design. As a result of this kind of professional knowledge of our engineer, without doubt, with the development of same SoC schedule photograph is compared, design of this kind of SoC will be the fastest, because power source management is by design group first compositive and without any support. We have confidence to make sure this one the fastest TTM can help a client decide compose builds energy-saving SoC, in order to answer the mature market that like content couplet net such rising market and energy efficiency demand become crucial (car, consume an electron. . . . . . ) .

 

Graph 7: Complete power source runs IP market

 

Clock allocation

 

Our clock IP allows to come true from beginning to end region of on-line power source, the job below threshold value voltage can be approached in 32 KHz. According to target clock precision, clock source can be those who be based on crystal or be based on RC. RC and XTAL oscillator also can be combined together, in order to ensure of RC oscillator start quickly, the switch after moving next arrives XTAL oscillator.

 

Because the electric current of RAM maintains,become scale with voltage, because this will receive the operation of electrify source region from beginning to end,be close to RAM as far as possible (MDRV) the least data maintains voltage, the lowermost power comsumption that can ensure SoC Morpheus mode falls. Our manostat library includes to exceed regulator of voltage of small static state, its but depress of report of process designing output comes 0.6 V, its consult voltage does not exceed 150 NA.

 

Effective implementation power source manages requires professional knowledge

 

The place before be like is narrated, important is a reappraise this, handling electric power (control, the door accuses or allocate) when, professional knowledge is crucial. Those people that participate in SoC number design are a few more compositive imitate function, they know to be when compositive imitate must special caution! I discuss imitate to design not only (the task that this is an expert apparently) , and still involve clock and power allocation, and signal integrality protection. Power source management carries out special likeness, have technology and the design that professional knowledge just can assure first time is right only only.

 

This is why on the basics that the technology that we offer in PM expert supports, the attempt helps their client further through developing mature method, the development of the EDA tool that this translate into manages on power source especially, the target is the power source framework with determinism ground right choice and IP component. These are test version, solved all power source management to implement measure:

 

● PowerArchitect allows to explore all sorts of power source frameworks and select optimal job site;

 

● PowerDesigner is an automation tool, use at generating top class UPF, the RTL of top class RTL and ACU, the MAESTRO module UPF that uses top class RTL designs compose to build;

 

The SoC that ● PowerVision is drive of integrality of a kind of power source emulates a tool.

 

Processing power source manages and allocating is a very formidable task, and very intractable! With the number the design differs, developing complete SoC (too big) when, IP of nonexistent test and verify (VIP) emulate with moving imitate (SPICE) . In addition, can we ask digital stylist manages imitate to emulate? But the integrality that decides wrongly to may affect crucial signal a little is made when choosing power unit. The optimal method that implements power source management in the safety in SoC is the professional knowledge of the engineer that the inquiry has knowledge of this domain major, will conduce to establish framework of optimal power source, carry out power source management, make your SoC becomes efficient and energy-saving thereby.

 

Epilogue

 

To chip manufacturer, tall chip power comsumption now is the true attention of any domains orders electronic trade. 2000 around, the wireless shift that solution of complex power source government is in only is carried out in application, instantly, for content couplet net, car or consume kind of application to carry out these solutions to become very necessary.

 

But, efficient power source management comes true in SoC, complex to may be being considered as for the SoC framework division of use SoC framework first and have a risk. Very complex, because he discovered all sorts of functions, basically be imitate function, and he had not been accepted choose in SoC and come true its groom. The risk that design plan affects when why is this making a wrong choice namely is true, the main risk that causes the trade that missed this rapid development – appear on the market time (TTM) .

 

We developed a complete unit library, use at power source administration achieving in SoC (voltage regulator, interface of power source region is called, distribution, clock allocation) . We are to sell this library not just, still can take action in the begining in the project, through providing seasoned SoC framework expert (SAE) technical support, framework of power source of SoC of definition of help design group and executive strategy.

 

The article is reprinted observe from semiconductor industry.