Brief introduction

The content that how many there are to design ” about “ADC bumper on the network had you examined? The answer is more than 4 million, find the content that we need very hard in so many bibliographical reference. Collect a system to design an engineer to most imitate and mixture signal data for, this may not be very accident, because the design does not have amortize modulus converter (the exterior front of ADC) needs to have patience and many proposal. It often is regarded as a kind of artistic form, it is the reservation of the eccentric Great Master that masters its doohickey through fumbling for years. To the person without experience, the iteration that this is a dismay making a person tries a process. Most moment, because the norms requirement of mutual correlation is very much, force design personnel to must have a lot of balance (and evaluate) ability achieves optimal result.

 

Challenge

The design of amplifier class is comprised by two different level related each other, because this problem becomes,build a model on maths hard, especially because have nonlinear element and this two class are relevant. The first pace is to choose to use the amplifier that amortize sensor is outputted and drive ADC inputs. The 2nd pace is to design low connect filter to input bandwidth in order to reduce, thereby utmost ground reduces the noise outside the belt.

 

Ideal amplifier is to offer just good bandwidth with correct amortize sensor or change send implement the signal of generation, and won’t increase additional noise, and power comsumption is 0, but actual amplifier and this apart are very far. Below most circumstance, amplifier norms will decide integral system performance, be in especially noise, lack fidelity with power comsumption respect. To clear up a problem better, the first pace is the working principle that understands disperse time ADC.

 

Disperse time ADC obtains the sample of signal of consecutive time imitate, change its amount to word to pile up next. When signal by sampling when, according to the type of imitate converter, same and inherent problem has two kinds of different cases.

 

SAR ADC is compositive a sampling maintains implement, its basically are comprised by a switch and a capacitance, action is to maintain imitate signal to be finished till changeover, if pursue,1 is shown.

 

Graph 1. Sampling carries circuit plan

 

Disperse time Σ-ΔADC or crossed sampling converter to achieve similar input step, have the input switch of certain and in-house capacitance namely. Σ-ΔThe sampling mechanism of ADC differs somewhat, but sampling input framework is similar, use switch and capacitance will maintain imitate to input the carbon of signal.

 

Below these two kinds of circumstances, switch is to use CMOS craft implementation, the resistor when closing is be not 0 values, it is a few ohm normally. Resistor of this series connection and sampling capacitance (PF class) combination, mean ADC to input bandwidth often very big, want below a lot of circumstances ambitious at ADC sampling frequency.

 

Bandwidth problem

To converter, inputting signal bandwidth is a problem. In sampling theory, we know Kui of prep above Nai this special frequency (the half of ADC sampling frequency) frequency signal should be moved to divide, these frequency signal will produce a mirror in target frequency band or mix otherwise fold. Normally, have in noise spectrum quite Kui of Nai of ADC of consist in of one part power this special in the frequency band of frequency above. If do not handle this kind of noise, it will be mixed fold Nai Kui this special frequency is the following, increase background noise (like the graph 2 are shown) , make dynamic limits of the system is reduced apparently.

 

Graph 2. Nai Kui this special fold mirror

 

ADC inputs signal bandwidth, and bumper outputs bandwidth, it is the first problem that should solve. Fold to ensure noise won’t be mixed downward, must restrict ADC to input the bandwidth of signal. This is not a small issue.

 

Normally, the choice of amplifier is to be based on big signal bandwidth (press namely place rate) the norms that accumulates with gain bandwidth, so that answer the extreme circumstance that inputs signal, the signal of the sharpest change that this decided to ADC can dog.

 

However, the effective noise bandwidth of amplifier is equal to small signal bandwidth (consider in the light of the signal that is less than 10 MV P-p normally) , this often compares tower above of big signal bandwidth at least 4 to fivefold.

 

In other words, if big signal norms is in the light of 500 KHz choice, bandwidth of so small signal can achieve 2 MHz or 3 MHz very easily, this may bring about ADC to collect a large number of noise. Accordingly, before inputting imitate signal ADC, should be in bandwidth of exterior limitation small signal, the noise that measures otherwise will be norms of ADC data manual 3 arrive fourfold.

 

Graph 3. Inphase amplifier is configured

 

Express 1. The noise that amplifier amount to carries to output, RTO

 

 

Remember, the thermal noise that amplifier produces depends on amplifier gain and total system bandwidth. Circuit give typical examples is shown 3 times like the graph, noise source summary is in watch 1 in, among them:

 

T is temperature (the unit is K) ,

 

K thises for Bo Er graceful constant (1.38×10−23 J/K) ,

 

Resistance unit is Ω ,

 

BW points to small signal bandwidth.

 

Above formula makes clear, what increase to have enough attenuation property before ADC input cites a base is low connecting filter is in order to make sampling noise the least very important, because the square root of noise and bandwidth becomes scale. Normally, use schism resistor and capacitance implementation to end frequency is enough low first-order low connect filter to be able to eliminate major broadband noise. First-order low connect filter to still have an additional profit, reduce the scope of any other bigger signal besides target frequency band namely, prevent its to arise possibly by ADC sampling mix fold.

 

But, this has not been over. Resistor of ADC in-house switch and capacitance defined imitate to input bandwidth, but because input the change of signal, meeting generation time domain fills discharge loop. Every time switch (the exterior circuit that receives sampling ADC capacitance repeatedly) when closing, in-house capacitance voltage likelihood and store before the voltage on sampling capacitance is different.

 

Why be reactive problem?

A classic imitate problem is below: If “ has two shunt-wound capacitance to receive a switch repeatedly, when switch disconnects, a capacitance stored a few energy, so when switch closes, what can two capacitance produce? ”

 

The answer depends on charge the rate between the energy that capacitance stores and capacitance. For example, if two capacitance have same value, criterion energy will be equational between them, the voltage that measures between capacitance terminal halve, if pursue,4 are shown.

 

Graph 4. Charge (left) and did not charge (right) capacitance

 

This is reactive problem.

 

A few ADC can carry out in-house calibration in order to compensate in-house error, this is called from firm 0 calibration. These programs can make sampling capacitance voltage is close to power supply course or another voltage, for example the half of fiducial voltage.

 

The exterior signal that this means amplifier amortize and sampling capacitance (its must save imitate to so that get new sample book,be worth) often not be to be in same potential (voltage) . Accordingly, sampling capacitance must charge or discharge, in order to make its and bumper output have same potential. The energy that this process place requires will come from exterior capacitance (the capacitance in the low filter that connect RC) with exterior bumper. Of repartition of this kind of charge and voltage build the time with will need proper, during this the voltage of each bits of place in circuit will be disturbed, if pursue,1 is shown. The charge amount of repartition may be very large, be equivalent to electric current flowing into or pour out of amplifier and flow into capacitance.

 

The result is amplifier shoud be able to be quite inside very limited time right low the sampling capacitance of the exterior electric capacity that understands filter and ADC undertakes charging / discharge, resistor of the low wave that connect filter can use as current limliting implement.

 

More specifically, amplifier shoud be able to be mixed from sampling capacitance inside assigned error limits quite exterior source charges to capacitance / discharge. Exterior low the cut-off that connects filter frequency should compare target frequency band slightly a bit taller, change by the poorest condition between the digit of the time constant of filter, ADC and example (namely we shoud be able to quite accurate those who measure is the poorest input rank is jumped) will define.

 

How to solve reactive problem?

The simpler method that solves this problem is to choose to have enough pressure place rate, bandwidth the amplifier of gain of gain accumulating, open loop and CMRR, the largest electric capacity that can find you in the market is put in output end, and resistor is enough small, in order to satisfy low understand filter bandwidth requirement.

 

Because electric capacity is very large, reactive problem will be negligible not plan, bandwidth suffers low know filter limitation, so the problem is able to solve, right?

 

Very regretful, the solution above won’t be successful, but if you are very good strange, want to attempt afore-mentioned solutions, so you can discover at 2 o’clock: Electric capacity will be so large like condensed milk container, amplifier does not like to output end to have empty ministry impedance.

 

The function of amplifier depends on the empty ministry impedance that amplifier sees. Below this kind of circumstance, low the weakness that understands filter is THD and set-up time function are reduced. The addition of set-up time will bring about amplifier to cannot charge to capacitance, make the voltage of ADC sampling is not correct final voltage. What this outputs aggravate ADC is nonlinear.

 

To elaborate the viewpoint above better, graph 5 showed amplifier drive is different the function difference of block sex load. Graph the 6 small signal that showed the load that allow a gender is caused are too strong, this meeting affects set-up time and degree of linearity.

 

Function of graph 5.AD4896-2 THD and laden relation

 

The small signal of graph 6.ADA4896-2 is transmitted answer the concern with load

 

Solve this problem for utmost ground, amplifier output should be passed low the series connection resistor that connects filter and exterior capacitance segregation.

 

Resistor should enough big, in order to make sure bumper won’t see empty ministry impedance, but enough small, in order to satisfy the input system bandwidth that place requires, the IR that the electric current that makes bumper is poured out of causes on resistor is pressed fall the smallest (amplifier is likely cannot enough make stability of this kind of voltage drop comes down quickly) . In the meantime, resistor should support exterior capacitance to be reduced enough little value, with the smallest change recoil and do not affect set-up time.

 

You can find more information here.

 

Fortunately, a few tools can let us forecast the assorted performance of ADC, amplifier and filter, e.g. tool of accurate ADC driver.

 

This tool can be mixed to reactive, noise lack fidelity function undertakes emulation, if pursue,7 are shown.

 

Graph 7. All sorts of emulation of tool of accurate ADC driver

 

Low the experience rule that knows filter

Normally, first-order low in connecting filter to appear in a lot of proposals, but why to use more high-ranking filter without the person? Unless apply specific requirement to eliminate the interference outside the larger area in inputting signal or harmonic, increase filter otherwise rank number will bring additional complexity to the system. Generally speaking, eclectic plan is to let small signal bandwidth demand of summary prep above, this meeting affects noise, but advantage is can relaxed drive ADC inputs class, can reduce power comsumption and cost.

 

Reduce a burden

Our premise arrives, amplifier does not like empty ministry impedance and / or provide big electricity, but this is inevitable, because capacitance brings empty ministry impedance, and capacitance can solve reactive problem.

 

The only way that improves this kind of condition is to reduce recoil. This kind of solution already was used by newest ADI converter, for example AD7768 and AD4000.

 

Because converter framework is different, the solution that every kinds of parts of an apparatus employs is different also. AD4000 SAR ADC is inputting the job below the power source of limits under imitate. Adoption solution calls tall block pattern, apply to the sampling frequency under 100 KHz only.

 

In AD7768, power source is equal to or prep above imitate inputs limits. The solution that AD7768 employs is called charge beforehand bumper, as contrary as tall block mode, its job frequency is highest can amount to ADC frequency of the biggest sampling.

 

Two kinds of solutions all are based on same working principle, the main difficulty of drive ADC is capacitance charge repartition. In other words, join afresh when in-house switch when sampling capacitance, input bumper and low the voltage drop that connects filter to see is smaller, voltage recoil is smaller, ADC inputs electric current to be reduced accordingly. Accordingly, drive ADC is easier, set-up time is shorter also. On filter resistor pressure fall reduce, reason communication function gets promotion.

 

Graph 8 showed charge beforehand bumper and tall block mode make can with ban be opposite with the circumstance the influence that inputs electric current.

 

Graph 8. Input electric current

 

Input electric current is taller, amplifier bandwidth also should be jumped over tall (jump over namely fast) . Accordingly, the input is low a filter bandwidth should be taller, this meeting affects noise.

 

For example, to inputting signal with the 1 KHz of 1 MSPS sampling, use SINAD will evaluate performance. End in different filter below frequency, the result that we get is like a graph 9 are shown.

 

Graph 9. Use and do not use tall block pattern the AD4003 SINAD below two kinds of circumstances and the relation that input bandwidth

 

The graph shows on, compare at identical configuration but tall block mode is shut, low input electric current (open of tall block mode) reduced filter to end the IR of frequency requirement and filter resistor is pressed fall, promoted ADC property.

 

From the graph 9 can observe, through raising an input filter ends frequency, exterior amplifier can charge quickly to sampling capacitance / discharge, but cost is noise can rise. For example, when open of tall block mode, the sampling noise when 500 KHz is less than the sampling noise when 1.3 MHz. Accordingly, SINAD is better when 500 KHZ inputs bandwidth. In addition, low the electric capacity that understands filter place to need can be reduced, conduce to the performance that improves amplifier drive.

 

Circuit designs an advantage

 

Come true in ADI company newest ADC these more easily drive or the character that reduce a burden, have a few major effects to whole signal catenary. ADC design personnel introduces issue of a few drive the crucial dominant position of ADC chip itself, depend on this solution can designing the signal to satisfy ADC efficiently as far as possible to ask, solve a few problems thereby, include to input bandwidth and amplifier stability.

 

Reduce the electric current that flows into ADC to input end, reduce recoil thereby, the voltage that means amplifier to want to handle rank jump inferior, but still have as identical as input of standard switch capacitance complete sampling cycle.

 

Reduce what should build inside time surely rank jump voltage, with use will more for long build bigger rank jump a meaning identical. Net effect is amplifier does not need so wide bandwidth to build the input adequately same and final cost now. Bandwidth is reduced mean amplifier power comsumption normally lower.

 

This kind of circumstance still has regard a kind of means: Imagine, think to make give ADC to input built amplifier without enough bandwidth normally, can be in now make can charge beforehand the implementation below the circumstance of bumper is built adequately.

 

AN-1384 of ADI application note introduced a series of amplifier to cooperate function of the realizable when using with AD7768 below mode of 3 kinds of power comsumption. One of amplifier that this documentation introduces are ADA4500-2, should not use charge beforehand when bumper, it is in hard in make the input of AD7768 is built below power mode (THD>- 96 DB) . But, should make can charge beforehand when bumper, function promotes excel significantly – 110 DB THD.

 

ADA4500-2 is amplifier of bandwidth of a 10 MHz, issueing the bandwidth that makes AD7768 builds place to need to be 12 MHz about to calm mode, we see, support uses easy drive performance now amplifier of this kind of inferior bandwidth. Accordingly, these character make the design of front amortize circuit more easy not only, and still allow freer land to choose yuan of parts of an apparatus to be restricted in order to maintain to be worth limits in systematic power comsumption or heat inside.

 

Flow into ADC imitate to input the 2nd advantage that the electricity that makes a base reduces, it is to had shed series connection resistor now (its use as the one part that inputs RC network) electric current is reduced.

 

To traditional ADC input, mean relative to bigger electric current can use little value resistor only, can produce very big voltage drop on this resistor otherwise. Here press greatly gain error or linear error appear in falling to bring about ADC possibly to change an outcome.

 

However, use lesser resistance to also have a challenge. Use lesser resistor to realize identical RC bandwidth to mean should use larger electric capacity. But, this kind

 

The electric current that when using easy drive performance, encounters reduces a circumstance, mean can use be worth resistor greatly and won’t affect performance relatively, can ensure the system is stable.

 

Circuit performance dominant position

 

The circuit that place of consideration above paragraphs narrates designs an advantage, apparent, use these character to still can obtain performance dominant position or the chance that improve performance further.

 

The advantage that has mentioned, can use inferior bandwidth amplifier to achieve better performance namely, also can use at expanding more the function that optimizes a system. For example, even if is the input signal that builds adequately already, should build finally when happening, still may exist between the input a few do not match. Accordingly, make can charge beforehand the character of bumper and so on will mean this kind to be built finally the conference is small much, can realize the THD of top level so, and this is impossible before.

 

The electric current that has shed resistor of RC network series is reduced also be helpful for function. In addition, input electric current to be reduced significantly not only, and it relies on input voltage scarcely. THD also can get ameliorative, because input pair of electrify block any do not match to be able to bring about ADC to input end to see lesser voltage is poor, and voltage drop does not have signal dependence.

 

Inferior input electric current is harmonic to breaking gain precision is influential also. Because absolutely electric current is reduced, and the voltaic change related signal decreases, the component value change on every passageway or every circuit board brings about the possibility that breaks harmonic gain error to produce bigger change lesser also (manage together, the voltage decrescent that inferior electric current brings about series connection resistor to go up) . Use charge beforehand bumper can come true better break norms of harmonic gain error absolutely, the function that circuit board or passageway differ inside the system also is met more consistent.

 

In the system that demand is collected to get used to different signal in ADC sampling rate and changes, collect card in data for example in, inferior electric current still has another profit. Charging beforehand below the circumstance of bumper, the voltage drop that inputs passive component to go up changes along with the sampling rate of ADC, because be below taller sampling rate, ADC inputs capacitance to regular meeting charges often and often discharge. This applies to imitate to input method and fiducial input method at the same time, this voltage change regards ADC general as to lose harmonic gain error relevantly with sampling rate.

 

But, should make can charge beforehand when bumper, absolutely electric current and corresponding absolutely voltage drop are in the conference is small in the begining much, the voltage change that because rate of this ADC sampling changes,causes also is met low much. In final system, this is meant need new calibration system to lose harmonic gain error not quite when adjusting sampling to lead, and lose harmonic gain error so not sensitive to the change of ADC sampling rate.

 

Cost advantage

One of main good points of easy application characteristics are concerned with totle drilling cost. The design of each respect and performance dominant position bring about development cost is reduced likely with moving cost.

? Simpler design means design workload to decrease, the time that finishs the first prototype is faster,

? The machine rate that archetypal design succeeds is older.

? Easy drive performance supports lower bandwidth, can use the amplifier of inferior cost consequently.

? Break harmonic gain advantage to be able to reduce factory calibration.

? Performance improvement can reduce spot calibration or press need calibration, decrease thereby machine down time and / or raise yield.

 

The example of use AD7768-1

Watch 2 in showing AN-1384 application takes notes a few measure data, this data conduces to design personnel choosing appropriate amplifier to come drive AD7768-1 ADC. The example in form explains, should make can charge beforehand when character, improve range quite apparent. Specific for, the improvement of THD is above mention reduce ADC together with the result of the integrated effect of the burden at drive circuit. For example, should make can charge beforehand when bumper, the configuration that uses ADA4945-1 amplifier makes THD raises 4 DB. Similar, ADA4807-2 circuit makes THD increases 18 DB. These example make clear: High-powered amplifier, when the easy drive performance that provides with a lot of newest ADC of ADI company is united in wedlock, can achieve top-ranking performance level.

 

Express 2. Use the AD7768-1 property of different amplifier
 

 

Conclusion

Because the recoil of converter and bandwidth ask, design a drive to be not easy thing without the circuit of amortize ADC, need proper method and eclectic consideration. A lot of moment, the function of the respect such as the THD that needs circuit to will decide integral system, SNR and power comsumption.

 

The newest and accurate converter that ADI company uses SAR and Σ-Δ technology is compositive a series of character, but utmost ground reduces converter to input electric current. This will make recoil the smallest, decrease greatly and simplify exterior circuit, the norms that cannot come true before implementation is numeric. SAR and Σ-Δ technology consequently more use easily, project time is able to shorten, systematic character gets ameliorative.

(origin: Yadenuo semiconductor, author: Stuart Servis and Miguel Usach Merino)