In the process of FOC control development in electric machinery drive, whether had you encountered electric machinery noise to pass the case that cannot on the low side of big, efficiency run even? All these results from likely the sampling of phase current is unusual, correct three phase current cannot rebuild in bringing about FOC algorithm thereby! Small the source of defer of an element —— that makes up here to analyse sampling of influence electric current to everybody!

 

1.Foreword

 

In the control of FOC of electric machinery drive of double resistor sampling, the intermediate hour that sampling nods a setting to be opened for the canal below drive axle. Attention, here is the intermediate hour that the canal below drive axle opens, among the PWM cycle that is not MCU output always. Because from MCU computation generates PWM to send the ADC of MCU module to voltaic signal, this typical drive develop attacks in, existence amounts to 7 defer source!

 

 

 

2.Defer type reachs typical time

The 7 defer source that form points to to in understanding develop of system of electric machinery drive to attack, exist in detail below reachs its typical time. These defer are together overlay, the influence of generation is: Undee lag of actual output PWM anticipates at MCU computation the PWM of output is undee, according to this computation, dot of phase current sampling needs lag to anticipate the intermediate hour of the PWM weaveform of output at MCU computation.

 

 

3.Defer source labor

Time of 3.1PWM dead band is inserted

 

Do not have in three-phase in brushing system of electric machinery drive, need 3 bridges arm to control flow direction of look line electric current, there is two powers parts of an apparatus on every bridge arm, be like MOSFET, IGBT. This cannot guide at the same time to power parts of an apparatus, can appear otherwise the circumstance of short circuit. Here explains with MOSFET as power parts of an apparatus. In control, must insert dead band time to open position in order to ensure upside and bottom MOSFET won’t are in at the same time. The typical cost of dead band time may arrive in 100ns between 2μs, specific depend on all sorts of elements in the system, be like model of MOSFET driving voltage, MOSFET.

 

After the PWM weaveform that needs in place inserts dead band time, what we get is PWM midpoint moves right with ascendant edge. Accordingly, in FOC control algorithmic computation gives proper PWM later, we begin to see the first defer instantly, namely dead band time.

 

 

Defer of 3.2 smooth Ou and beforehand driver defer

 

In MCU control FTM module outputs PWM weaveform to get pilot to MOSFET grid that momently between, all sorts of smooth electric coupling and beforehand the signal of driver is answered caused additional delay.

 

With MCU the undee photograph of the output that cite a base is compared, beforehand the output defer of driver period of time (Delay1) .

 

 

Defer of 3.3 transistor switch

 

Through beforehand after driver, PWM weaveform arrives at MOSFET transistor, but because its are inherent characteristic, all transistor need proper time to guide connect and end. Reach according to transistor category guide / end between the voltage n that switch place needs, this defer time differs somewhat.

 

Delay2 is nodded for switch of theory of photograph line voltage (CMP2) the whole defer between the hour that nods with actual switch.

 

 

Finally, grid voltage arrived to be able to make transistor guides the extent that know, electric current passes look line and sampling resistor, in sampling resistor two end produce voltage difference, gules weaveform is the phase current weaveform below good position. Total time is like the delay of existence of PWM periodic midpoint that makes with MCU computation right now ” of shift of midpoint of phase current of the “ in the graph.

 

 

3.4 other defer

 

Following plan institute are shown, the final defer catenary that affects voltaic sampling is what change rate, MCU to bring a foot to go up by amplifier is low connect filter and ADC to change rate to form. The hour that labels with red circle in the graph is correct voltaic sampling hour, can see, the PWM midpoint photograph that outputs with FTM is compared, phase current sampling is nodded greatly defer.

 

 

4.Epilogue

 

In all electronic circuit, can put in the delay problem of signal. Signal defer is impossible to be eliminated completely, but can affect in order to reduce through choosing the parts of an apparatus of low defer.

 

In electric machinery drive, besides choosing appropriate parts of an apparatus, still need to undertake to signal defer software is compensated. The accurate defer time of these defer sources that allude in article, we can reach through oscillograph and computation, these defer are compensated on software, caikede gives correct voltaic sampling hour. The data ability that collects in correct hour so regards FOC as the data origin that electric current of electric machinery three-phase rebuilds in control.