[introduction] JESD204B is the JEDEC standard that approves recently, the serial data interface that is used between converter and parts of an apparatus of several word processing. It is the 3rd acting standard, solved a few blemish of previous edition. The advantage of this interface includes: Data interface road needs circuit board space by place fewer, build with maintain sequential the demand is lower, and of converter and logistic parts of an apparatus enclose smaller. The new-style imitate of much home supplier / digital converter uses this interface, for example the AD9250 of ADI.

JESD204B is the JEDEC standard that approves recently, the serial data interface that is used between converter and parts of an apparatus of several word processing. It is the 3rd acting standard, solved a few blemish of previous edition. The advantage of this interface includes: Data interface road needs circuit board space by place fewer, build with maintain sequential the demand is lower, and of converter and logistic parts of an apparatus enclose smaller. The new-style imitate of much home supplier / digital converter uses this interface, for example the AD9250 of ADI.

Compare with existing interface format and consultative photograph, JESD204B interface is more complex, more delicate, must overcome a few difficult ability to achieve its advantage. Like other level, should make this interface occupies rate or double multiple to wait for commonly used interface according to rate CMOS/LVDS than odd multiple more welcome, it must can not have the job that seam the ground. Although JESD204B standard is made by JEDEC, but certain and specific information still needs to clarify, distribute possibly perhaps in many bibliographical reference. Additional, if a compendious guideline can show this standard, work summarily principle and how to remove trouble, be opposite undoubtedly the person that use will be very helpful.

The interface of the ADC of standard of article illuminate JESD204B and FPGA, judge its to whether work normally, and may more important is, if why remove trouble when having a problem. The trouble removal technique that discusses in article can be used commonly used test and measure equipment, include oscillograph and logistic analyzer, and Xilinx? ChipScope or Altera? the software tool such as SignalTap. At the same time explain understands interface signal to transmit, so that can use a kind or what a variety of methodological implementation signal transmit is visible.

JESD204B overview

The means that JESD204B standard provides a kind to process converter of one or more data and digital signal interface of parts of an apparatus (it is ADC or DAC and FPGA interface normally) , compare at normally collateral data is transmitted, this is the serial interface of a kind of higher rate. This interface speed is as high as 12.5 Gbps/ passageway, serial data link reachs use frame embedded clock and to neat character. It reduced the amount taking a line between parts of an apparatus, reduced walk along a line to match a requirement, eliminated build with maintain sequential to restrain a problem, simplified thereby of interface of data of high speed converter carry out. Because link needs to be built before data is transmitted, because this is put in new challenge, must use new technology to decide whether interface works normally, and how to do when interface breakdown.

JESD204B interface establishs synchronous link through 3 phase: Code group is synchronous (CGS) , initiative passageway is synchronous (ILAS) and data transmit level. Link needs the following signal: Share referenced clock (clock of parts of an apparatus) , electrical continuity bonding of data of physics of a CML that need branch (call ” passageway ” ) , and an other and synchronous signal (SYNC~ and likely SYSREF) . Use what signal to depend on subclass:

? Clock of 0 use parts of an apparatus, passageway mixes subclass SYNC~ .
? Clock of 1 use parts of an apparatus, passageway, SYNC~ mixes subclass SYSREF.
? Clock of 2 use parts of an apparatus, passageway mixes subclass SYNC~ .

Subclass 0 below a lot of circumstances enough satisfies requirement, it is the key of the article consequently. Subclass 1 with subclass 2 provided the means that builds determinism defer, this is in need is many more synchronous in parts of an apparatus or the application that need systematic synchronism or secure defer very important, the sampling edge with the foregone need of exemple a certain incident like a system, or a certain incident must answer input signal inside formulary time.

Graph 1 showed from emissive parts of an apparatus (ADC) arrives receive parts of an apparatus (of FPGA) simplify JESD204B link, data from an ADC by a passageway is transmitted.

Graph 1. JESD204B link pursues: An ADC passes a passageway and FPGA interface.

Although JESD204B standard has a lot of variable, but certain variable to link it is particularly important to build. These crucial variable are shown as follows (note: Do these values express to be “X normally? 1” ) :

? M: Converter number.
? L: Physics connects number of channels.
? F: 8 byte of every frame are counted.
? K: The frame of every many frame is counted.
? N and N ‘ : The digit that states converter resolution and every example is used respectively (the multiple of 4) . N ‘ the value is equal to N value to add control and fill data digit.

Subclass 0: With pace measure

As above, a lot of application can use relatively simple subclass 0 jobs mode, this also is to establish the simplest pattern with link of test and verify. Subclass 0 will build through 3 phase with monitoring synchronism: CGS phase, ILAS phase and data phase. The chart related each phase shows data with different pattern, can be in analyzer of fictitious I/O of oscillograph, logistic analyzer or FPGA (like Xilinx ChipScope or Altera SignalTap) on observe these data.

Code group is synchronous (CGS) phase

The CGS phase that can observe on link most substantial is shown 2 times like the graph, in the graph 5 highlight indication drop to explain as follows.

? Receiver cites a base through pulling low SYNC~ , issue a synchronous request.
? Send and receive implement begin from next symbol, send what did not increase trouble / K28.5/ symbol (every symbol 10) .
? What receive at least 4 inerrancy when receiver is successive / the synchronism when K28.5/ symbol, bring SYNC~ the foot to pull next tall.
? Receiver must receive character of 8B/10B of at least 4 inerrancy, otherwise synchronism will fail, link stays in CGS phase.
? CGS phases ends, ILAS phase begins.

Graph 2. 0 link signal is in JESD204B subclass the logistic output of CGS phase (have two channels suppose, a parts of an apparatus contains two ADC) .

/ K28.5/ character also is called in JESD204B standard / K/ , if pursue,3 are shown. The standard asks dc is balanced. Use 8B/10B code, can come true average and character is included wait for a quantity 1 with the balance alignment of 0. Every 8B10B character may be had (1 more) or negative (0 more) deviation, the odd even sex of current character is decided by the polarity deviation of the character that sends before, this is normally through be being sent alternately word of odd even sex and word of sex of negative odd even will come true. Showed in the graph / two kinds of polarity of K28.5/ symbol.

Graph 3. How does the logistic output of K28.5 character and it travel through method of JESD204B Tx signal.

The key notices the following:

? Serial value expresses 10 when transmit through the passageway logistic n, can see through measuring the oscillograph of physical interface.
? The logic that 8B/10B value represents to be transmitted through the passageway is worth (10) , can see through measuring the logistic analyzer of physical interface.
? The JESD204B before data value and data logic state 8B/10B codes is sent and receive implement the logistic n of the symbol inside module, can wait for FPGA logic to analyse a tool to see through Xilinx ChipScope or Altera SignalTap.
? The symbol expresses to want the hexadecimal value of sent character, notice the odd even sex of PHY layer.
? Character shows the JESD204B character that indicates in JEDEC standard.

ILAS phase

ILAS phase has 4 many frame, allow receiver to be opposite neat the passageway that comes from all link, and parameter of link of test and verify. The takes line and receiver to bring about character for harmonic and different length is deflective, the passageway must is opposite neat. 4 many frame are linked together closely (graph 4) . No matter enable parameter of the link that increase trouble, ILAS is to not have from beginning to end add faze to transmit.

Graph 4. 0 link signal is in JESD204B subclass the logistic output of ILAS phase.

SYNC signal turns into from low n after tall n, enter ILAS phase. Send module interior to dog (ADC is in-house) complete after much frame, begin to send 4 many frame. Fill data is inserted in needs character, so that convey complete much frame (graph 4) . 4 many frame include:

? Much frame 1: With / R/ character [K28.0] begins, with / A/ character [K28.3] ends.
? Much frame 2: With / R/ character begins, receive after / Q/ [K28.4] character, it is 14 link configuration parameter that configure 8 words next (express 1) , finally with / A/ character ends.
? Much frame 3: With much frame 1 identical.
? Much frame 4: With much frame 1 identical.

Graph 5. / K/ character [K28.5] , / R/ character [K28.0] , / A/ character [K28.3] and / Q/ character [K28.4] graph.

Express 1. The CONFIG of 2 expresses ILAS much frame (14 JESD204B configure parameter 8 words)

Frame length can use JESD204B parameter calculation:

(S) × (1/ sampling rate) .

Meaning:

(example is counted / converter / frame) × (1/ example rate)

Give typical examples:

Sampling rate is 250 MSPS, every frame every converter the converter of an example (note: In this exemple “S” is 0, be worth for the binary system by encode because of it – 1) , its frame length is 4 Ns.

Much frame length can use JESD204B parameter calculation:



Meaning:

(example is counted / converter / frame) × (frame is counted / much frame) × (1/ sampling rate)

Give typical examples:

Sampling rate is 250 MSPS, every frame an example, every many frame has every converter the converter of 32 frame, its are much frame length is 128 Ns.



Data phase (make can character is replaced)

Level is transmitted in data, be opposite through controlling character monitoring frame neat. In the terminal point of frame executive character is replaced. In data phase, data or frame are right neat won’t cause additional expense. Character is replaced allow to send pair of neat character in frame border point, the last character that only requirement is current frame can replace the last character that is on one frame. This is helpful for (occasional) affirm after ILAS alignment, change to Qi Wei.

When giving now to list a situation, can carry out character to replace to transmitter:

? If ban,used increase trouble, of frame or much frame the last 8 words that 8 words are equal to on one frame.
? If make can increase trouble, of much frame the last 8 words are equal to 0x7C, or of frame the last 8 words are equal to 0xFC.

Emitter and receiver maintain tally of much frame of a this locality severally (LMFC) , does it last does computation arrive (K) of F × ? 1, next retrace begins computation afresh to “0” (oversight interior word is wide) . Send to all transmitter and receiver communal (source) SYSREF, these parts of an apparatus use SYSREF restoration its LMFC, so all LMFC should is the same as each other pace (inside cycle of a clock) .

Release SYNC (all parts of an apparatus can see) hind, transmitter is in the next time (Tx) LMFC retrace 0 when begin ILAS. If setting of K of F × is proper, be more than (transmitter encode time) + (circuit transmits time) + () of receiver decipher time, receive data general to travel from the SERDES of receiver before next LMFC go out. Receiver will send FIFO data, be in next next (Rx) LMFC border begins to output data. The SERDES of emitter is inputted and this kind of foregone relation between receiver FIFO output calls determinism delay.

What respect can make mistake?

JESD204B can say is a complex interface standard, there are a lot of delicate places on the operation. Want to find out the reason that cannot work normally, need has good knowledge to possible scenario:

Be immersed in CGS mode: If SYNC maintains logistic low n; Or duration of pulse tall n is little at 4 many frame:

Check circuit board, not electrify:

? SYSREF and SYNC~ signal should shed coupling continuously.

? In circuit board not below the circumstance of electrify, examination from SYNC~ source (come from FPGA or DAC normally) input to SYNC~ (it is ADC or FPGA normally) link of circuit board SYNC~ is nice and have low impedance.

? Ensure next pulling or go up helping resistance is not the dominant element that signal transmits, for example: Value too small or short circuit can be brought about cannot correct drive.

? The poor cent that confirms JESD204B link is opposite line (reach cable, if use) match.

? The impedance needing branch that affirms a line is 100 Ω .

Check circuit board, electrify:

? If there is a bumper in SYNC method / converter, ensure it works normally.

? Affirm SYNC~ source is mixed board electrify road (SYNC+ and SYNC- , if be poor cent) configuration is proper, generation accords with SYNC~ to receive the logistic n that parts of an apparatus asks. If logistic n is incompatible, should check source and receive configuration in order to find out a problem, otherwise, seek advice from manufacturer of parts of an apparatus please.

? Affirm JESD204B serial transmitter is mixed board circuit configuration is proper, the correct and logistic n that generation accords with receiver of JESD204B serial data to ask. If logistic n is incompatible, the origin that should check circuit and receive configuration in order to find out a problem. Otherwise, seek advice from manufacturer of parts of an apparatus please.

Check SYNC~ signal:

? If SYNC~ is static logic n, link will stay in CGS phase. The likelihood is transmits data has a problem, or JESD204B receiver did not undertake correct decipher to example. Affirm those who send is / K/ character, affirm receive configuration setting, acknowledge SYNC~ source, examination board circuit, the consideration crosses drive SYNC~ signal and force link to enter ILAS mode, find out link thereby receiver and send and receive implement problem. Otherwise, seek advice from manufacturer of parts of an apparatus please.

? If SYNC~ is static logic tall n, affirm source parts of an apparatus configured SYNC~ logistic n whether correctly. Be pulled on the examination and next pulling resistor.

? If SYNC~ pulse turns into tall n, return condition of logistic low n next and duration is little at cycle of 6 many frame, criterion JESD204B link can advance from CGS phase ILAS phase, but can stay after one phase. This may be meant / K/ character is correct, the basic function of CDR is normal. Consult please part of ” of “ILAS trouble removal.

? If SYNC~ turns into tall n and duration is more than cycle of 6 many frame, criterion link can advance from ILAS phase data phase, but meeting after one phase malfunctions; Clew of relevant trouble removal consults please part of ” of ” data phase.

Examine serial data

Affirm send and receive implement the anticipation of data rate and receiver rate is same.

With tall impedance probe (if likelihood, use difference divides probe) measure a passageway; If character looks wrong, ensure the passageway differs cent to walk along a line to match, on PCB return method to was not interrupted, and parts of an apparatus solders correctly go up to PCA. With ILAS and data phase (look be like) random character is different, CGS character identifies very easily on oscillograph (if use rate enough tall oscillograph) .

With test and verify of tall impedance probe / K/ character.

? If / K/ character is correct, express link send and receive implement upright job is regular.
? If / K/ character is incorrect, express to send and receive implement parts of an apparatus or circuit board passageway signal has a problem.
? If shed coupling continuously, affirm transmitter and receiver in all modular voltage is inside the requirement limits of parts of an apparatus.

? The basis carries out a circumstance, emitter in all modular voltage limits may come for 490 MV 1135 MV.

? The basis carries out a circumstance, receiver in all modular voltage limits may come for 490 MV 1300 MV.

? The emitter CML difference that acknowledges data passageway to go up divides voltage (attention, CML difference divides voltage to be equal to signal of amplitude of each side voltage double) .

? To 3.125 Gbps and the following speed, emitter CML difference divides voltage limits to be 0.5 V P-p to 1.0 V P-p.
? To 6.374 Gbps and the following speed, emitter CML difference divides voltage limits to be 0.4 V P-p to 0.75 V P-p.
? To 12.5 Gbps and the following speed, emitter CML difference divides voltage limits to be 0.360 V P-p to 0.770 V P-p.
? The receiver CML difference that acknowledges data passageway to go up divides voltage (attention, CML difference divides voltage to be equal to signal of amplitude of each side voltage double) .

? To 3.125 Gbps and the following speed, receiver CML difference divides voltage limits to be 0.175 V P-p to 1.0 V P-p.
? To 6.374 Gbps and the following speed, receiver CML difference divides voltage limits to be 0.125 V P-p to 0.75 V P-p.
? To 12.5 Gbps and the following speed, receiver CML difference divides voltage limits to be 0.110 V P-p to 1.05 V P-p.
? If exist to add heavy option beforehand, should enable this option and observe the data signal on data method.
? The M that affirms emitter and receiver and L value are consistent, otherwise data rate may not match. For example, m = 2 and L = 2 the anticipation of this kind of circumstance is serial interface data rate is M = 2 and L = 1 the half of this kind of circumstance.
? Ensure the clock of parts of an apparatus that enters emitter and receiver already was locked up and frequency is correct.

If SYNC turns into tall n and make an appointment with 4 many frame continuously, stay in ILAS mode:

? Link parameter conflicts
? Affirm link parameter not deflection 1 (a lot of parameter regulations are decreased for the value 1) .
? Affirm ILAS much frame is deferent and correct, affirm send and receive parts of an apparatus, receiver the link parameter that with ILAS the more than 2nd frame conveys is correct.
? Computation anticipates ILAS length (Tframe, tmultiframe, tmultiframe) of 4 × , affirm ILAS already tried about 4 many frame.
? Affirm all passageway job is regular. Ensure nonexistent much passageway / much link conflict.

Enter data phase but link now and then meeting restoration (return CGS and ILAS phase first, reentrance data phase) :

? Periodic or take unoccupied place periodic SYSREF or maintain time of SYNC~ signal to disable.
? Link parameter conflicts.
? Character replaces conflict.
? The problem that increase trouble (if enable) .
? Passageway data attaint, noise or shake the likelihood forces a graph to close.
? Of stray clock or clock of parts of an apparatus had shaken big.

About eliminating the other and general clew of link breakdown:

? Run converter and link with permission lowermost rate, can use the low bandwidth that obtains more easily to measure an instrument so.
? Install combination of permission least M, L, K, S.
? Test pattern is used when the likelihood.
? Use subclass 0 will remove trouble.
? When removing trouble, ban with increase trouble.

This trouble removal guideline not end place is possible, but the engineer that knows more news to use JESD204B link and hope provided a very good basic framework.

Above is the overview of JESD204B standard, provided the economic information related link. The engineer that hopes to involve standard of this one newest high-powered interface can from which benefit, help somewhat to removing trouble.

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