The delay of power source starts circuit design and principle (Nuojiyaximen child version)

The delay of power source starts circuit design and principle (Nuojiyaximen child version)

[introduction] the domain is designed in telegraphic industry and microwave circuit, the end that uses MOS generally to be in charge of the Fonda that controls impulse current to be started to voltaic delay. MOS canal has guide an impedance Rds_on is low with the characteristic with simple drive, in all round add a few yuan parts of an apparatus can make the slow circuit that start. Although circuit is simpler, but the ability after the relevant switch that only MOS of have a thorough grasp provides is characteristic is right this circuit has thorough understanding.
 
The delay of power source starts circuit design and principle (Nuojiyaximen child version)
 
The article undertakes narrative from the enlightened process of MOSFET above all:
 
Although MOSFET is in the system of a few electrons such as control of switch power source, electric machinery,receive wide application, but a lot of electron engineers do not have process of very clear understanding MOSFET switch, and the condition with located in switch process MOSFET generally speaking, electronic engineer is based on grid charge to understand the enlightened process of MOSFET normally, if the graph shows this graph 1 times to be able to be checked in MOSFET data table
 
The delay of power source starts circuit design and principle (Nuojiyaximen child version)
Graph charge of 1 AOT460 grid is characteristic
 
The D of MOSFET is mixed S pole adds voltage to be VDD, the G that opens pulse to add MOSFET when drive is mixed when S pole, input capacitance Ciss charges, g is mixed linear of Vgs of S pole voltage rises and arrive at doorsill voltage VGS(th) , before Vgs rises to VGS(th) Id≈0A of leakage pole electric current, do not have leakage pole electric current to had flowed, the voltage of Vds maintains VDD changeless.
 
When Vgs arrives at VGS(th) , leakage pole begins to had shed voltaic Id, next Vgs continues to rise, id also rises gradually, when Vds still maintains VDD to arrive at Miller to make the same score stage voltage VGS(pl) when Vgs, id also rises to load current maximum ID, the voltage of Vds begins to drop from VDD.
 
During rice carves terrace, id electric current maintains ID, vds voltage is reduced ceaselessly.
 
Rice straps platform to end hour, id electric current still maintains ID, vds voltage reduces an inferior cost after Miller makes the same score an end, id electric current still maintains ID, vds voltage continues to reduce, but the slope that reduces right now is very small, the scope that reduces accordingly is very little also, the MOSFET after final stability can think because of this in Vds=Id×Rds(on) Miller makes the same score an end normally basically has guided.
 
To afore-mentioned process, understanding difficulty depends on why making the same score stage area in Miller, is the tension of Vgs constant? Drive circuit still provides drive electricity to grid, still charge to grid capacitance, why doesn’t the voltage of grid rise? And grid charge character is not intuitionistic to the enlightened process of the understanding MOSFET of figure accordingly, leakage pole will is based on to guide below an enlightened process of characteristic understanding MOSFET.
 
The leakage of MOSFET extremely guide a character and switch process.
 
The leakage of MOSFET extremely guide like if the graph shows MOSFET and dynatron 2 times,knowing character, apply at enlarge circuit when MOSFET, the base electricity that should use this curve to study its magnify character is dynatron is used only normally, collector electric current and enlarge are diploid, and electric current of voltage of MOSFET use grid, leakage pole and cross guide.
 
The delay of power source starts circuit design and principle (Nuojiyaximen child version)
Graph the leakage of 2 AOT460 extremely guide a character
 
Dynatron has 3 works area: End area, enlarge area and saturated area, MOSFET correspondence is to pass area, constant current area and attention of alterable resistance area: The G that division of MOSFET constant current also says saturated area sometimes or enlarge area opens pulse to add MOSFET when drive is mixed when S pole, when the voltage of Vgs lifts gradually, if the enlightened contrail A-B-C-D of MOSFET pursues 3 medium courses are shown
 
The delay of power source starts circuit design and principle (Nuojiyaximen child version)
Graph the enlightened contrail of 3 AOT460
 
Before debutting, place of MOSFET initial work is located in a graph the dot of right A playing role of 3, the VDD voltage of AOT460 is 48V, the voltage of Vgs lifts gradually, id electric current is 0, the voltage of Vgs achieves VGS(th) , id electric current from 0 begin to increase gradually
 
In the course that the process that A-B increases VGS(pl) from VGS(th) with respect to the voltage that is Vgs chooses to B from A, OK and special intuitionistic discovery, this process works the constant current area at MOSFET, namely the course that Vgs voltage and Id electric current seek a balance automatically, namely the metabolic partner of Vgs voltage varies accordingly as Id electric current, its change relation is MOSFET cross guide: Gfs=Id/Vgs, cross guide can check in MOSFET data table
 
What achieve load when Id electric current is the biggest when allowing voltaic ID, right now Vgs(pl)=Id/gFS of corresponding bar class voltage because Id electric current is right now constant, because tension of this grid Vgs is constant also changeless, see a picture 3 medium B-C, right now MOSFET is in relatively stable constant current area, the job the condition at amplifier
 
Before debutting, the voltage of Vgd is Vgs-Vds, for negative pressure, enter rice to carve terrace, the negative voltage absolute value of Vgd drops ceaselessly, over- 0 hind the voltaic majority that turns to press drive circuit for positive electricity has shed CGD, strap the charge of capacitance with broom rice, after accordingly the voltage of grid maintains changeless Vds voltage basically to reduce very low cost, the charge that rice straps capacitance basically by broom, pursue namely 3 medium C are nodded, then, the voltage of grid is in of drive electric current charge fall to begin to lift again, if pursue 3 medium C-D, make MOSFET guides completely further
 
C-D is alterable resistance area, tension of corresponding Vgs voltage is corresponding constant Vds voltage Vgs reachs maximum, vds voltage reachs the least value, it is ID as a result of Id electric current constant, be ID and MOSFET namely because of the voltage of this Vds guide the product of electrify block
 
The leakage that is based on MOSFET extremely when guiding the understanding MOSFET with a characteristic OK and intuitionistic curve debuts, span Mi Leping stage is the process that involves area, constant current area and alterable resistance area namely constant current area, MOSFET works at enlarge condition, id electric current is mixed for Vgs voltage cross guide product
 
Circuit principle defines:
 
MOS canal is voltage control parts of an apparatus, its extremely if capacitance equivalent circuit pursues show 4 times.
 
The delay of power source starts circuit design and principle (Nuojiyaximen child version)
Graph 4. The N of capacitance C2 MOS is received outside the belt circuit of equivalent of the capacitance between tubal pole
 
MOS is in charge of extremely Cds of capacitance of source of Cgs of capacitance of source of Cgd of capacitance of capacitance bar leakage, bar, leakage is OK decide by the following formula:
 
The delay of power source starts circuit design and principle (Nuojiyaximen child version)
 
The feedback capacitance Crss that the MOS in formula is in charge of, can check on the manual that input capacitance Ciss and the numerical value that output capacitance Coss are in charge of in MOS.
 
Capacitance fills discharge speed to decide MOS manages the speed that debut and closes, vgs charges to Cgs above all, as the rise of Vgs, make MOS is in charge of from end the area enters alterable resistance area. After entering alterable resistance area, ids electric current increases, but Vds tension is constant. Increase as the abidance of Vgs, MOS canal enters Miller to make the same score stage area, stage area is made the same score in Miller, vgs is maintained changeless, charge charges to Cgd, ids is changeless, vds is reduced continuously. Stage later period is made the same score in Miller, MOS canal Vds is very small, MOS entered saturation to guide period. Mix to ensure the changeover between MOS canal condition is linear foreseeable, capacitance C2 paralell connection is received to be on Cgd outside, if outside receive capacitance C2 to provide in-house bar than MOS leakage capacitance Cgd is a lot of bigger, can reduce MOS to be in charge of interior nonlinear the action when bar leakage of electricity allows Cgd to be changed between condition, can achieve additionally increase time of Mi Leping stage, the purpose of the speed that slow down voltage drops. Capacitance C2 is received to be used to outside the switch character that is in charge of to MOS as integrator undertakes be controllinged accurately. Controlled degree of linearity of leakage pole voltage to be able to control impulse current accurately.
 
Circuit description:
 
The graph shows what be in charge of to be based on MOS 5 times to restrict law circuit from impulse current of the active that start. The negative voltage that MOS is in charge of Q1 to be put in module of DC/DC power source inputs end, in electrify instant, the n of the 1st foot of module of DC/DC power source and the 4th base is same, control circuit to fall it to be pressed to negaive electricity by fixed rate next, the speed that voltage drops is decided by time constant C2*R2, this slope decided the biggest impulse current.
 
C2 can press the following and formulary make choice of:
 
The delay of power source starts circuit design and principle (Nuojiyaximen child version)
 
R2 by allow impulse current decision:
 
The delay of power source starts circuit design and principle (Nuojiyaximen child version)
 
Among them Vmax is voltage of the biggest input, cload is the summation of C3 and capacitance of interior of module of DC/DC power source, iinrush is the range that permits impulse current.
 
The delay of power source starts circuit design and principle (Nuojiyaximen child version)
Graph 5 active impulse current restricts law circuit
 
The delay of power source starts circuit design and principle (Nuojiyaximen child version)
 
D1 is diode of a stabilized voltage, with the bar source voltage that will restrict MOS to be in charge of Q1. Yuan R1 of parts of an apparatus, c1 and D2 are used make sure MOS is in charge of Q1 to maintain when firm electrify close position. Particular case is:
 
After electrify, the grid voltage that MOS is in charge of should rise slowly, arrive high when Vgs of bar source voltage after certain level, diode D2 guides, such all charge give capacitance C1 to charge with time constant R1×C1, vgs of bar source voltage rises with same rate, till MOS tubal Q1 guides a generation impulse current.
 
It is the formula of computational C1 and R1 below:
 
The delay of power source starts circuit design and principle (Nuojiyaximen child version)
 
Among them the voltage of the smallest doorsill that Vth is in charge of Q1 for MOS, VD2 is diode D2 guide is connected pressure fall, vplt is the bar source voltage when generating Iinrush impulse current. The product that Vplt can provide supplier place to offer in MOS is found in the data.
 
MOS provides an alternative
 
It is very important that the following parameter restricts the MOS of circuit to provide an alternative to active impulse current:
 
L leaks extremely puncture voltage Vds
 
Must choose Vds to compare the MOS canal with Vmax of voltage of the biggest input and even tall voltage of transient state of the biggest input, useful to communication system MOS is in charge of, choose Vds≥100V commonly.
 
Vgs of voltage of L bar source
 
D1 of stabilized voltage canal is the grid that uses protective MOS to be in charge of Q1 press puncture in order to prevent its too, the Vgs of bar source voltage of Q1 of apparent MOS canal must the voltage of the biggest retrorse puncture of D1 of canal of prep above stabilized voltage. The Vgs of bar source voltage that general MOS is in charge of is 20V, recommend the stabilized voltage diode of 12V.
 
L guides electrify block Rds_on.
 
MOS is in charge of must can the quantity of heat that dissipation guides electrify block Rds_on causes, formula of hear rate computation is:
 
The delay of power source starts circuit design and principle (Nuojiyaximen child version)
 
Among them the electric current of the biggest input that Idc is DC/DC power source, idc decides by the following formula:
 
The delay of power source starts circuit design and principle (Nuojiyaximen child version)
 
Among them the power of the biggest output that Pout is DC/DC power source, vmin is voltage of the smallest input, η is inputting voltage to output the efficiency when power is Pout for Vmin for DC/DC power source. η is OK check in the data manual that offers in supplier of DC/DC power source. The Rds_on that MOS is in charge of must very small, what it causes pressure fall and input voltage photograph is more negligible than ability.
 
The delay of power source starts circuit design and principle (Nuojiyaximen child version)
Graph 6. Active impulse current restricts circuit to be inputted in 75V, DC/DC outputs the weaveform when carrying for nothing
 
Devise give an example
 
Foregone: Vmax=72V
 
Iinrush=3A
 
Choice MOS is in charge of Q1 to be IRF540S
 
Choose diode D2 to be BAS21
 
Press formula (4) computation: C2>>1700pF. Choose C2=0.01μF;
 
Press formula (5) computation: R2=252.5kW. Choose R2=240kW, choose R3=270W<
 
Press formula (7) computation: C1=0.75μF. Choose C1=1μF;
 
Press formula (8) computation: R1=499.5W. Choose R1=1kW
 
The graph is shown 6 times for the graph the actual measurement of 5 circuit is undee, among them output of DC/DC power source is carry for nothing.
 
 

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