1, foreword

Electrostatic discharge (ESD – ElectroStatic Discharge) can bring ruinous consequence to electronic parts, it is one of main reasons that create integrated circuit be no longer in force. Develop ceaselessly as integrated circuit craft, the measure of CMOS circuit is ceaseless and narrow, the bar oxygen ply of pipe is thinner and thinner, the area scale of chip is larger and larger, MOS is in charge of can susceptive electric current and tension are less and less also, and the use environment of periphery was not changed, want what optimize circuit further to fight ESD function accordingly.

 

How to make complete chip effective the area fights ESD function smally, high as far as possible and the issue that does not need to increase extra craft step to become IC architect to basically consider.

 

2, ESD protects a principle

The design purpose of ESD protection circuit should avoid working circuit to become namely damage because of ESD, make sure in random two chip bring the ESD that happens between the foot to low block bypass introduces ESD electric current power supply cord. Bypass of this low block not only the electric current that wants to be able to absorb ESD place to arise, even Qian the voltage of working circuit, prevent working circuit to be damaged as a result of voltage overload. When circuit works normally, fighting electrostatic structure do not work, this makes ESD protects circuit to still need to have very good stability, can answer quickly when ESD happening, protecting circuit while, fight electrostatic structure oneself to be not damaged. The negative effect that combats electrostatic structure (input defer for example) must be inside the limits that can accept, prevent to fight electrostatic structure to produce latch.

 

3, the design of structure of protection of CMOS circuit ESD

Major ESD electric current comes from circuit exterior, because this ESD protects circuit,general design is by PAD or I/O circuit is in-house. Typical I/O circuit by output drive and input receiver two parts are comprised. ESD guides through PAD chip is in-house, accordingly all is linked together directly with PAD parts of an apparatus in I/O need to build to it bypass of parallel ESD low block, introduce ESD electric current voltage line, distributing by voltage line again chip each pin, reduce the effect of ESD. Specific to I/O circuit, it is the output drive that is linked together with PAD and input receiver, must assure to be when ESD happening, form the low block access that runs paralell with protective circuit, bypass ESD electric current, and can instantly effectively Qian protective circuit voltage. And when this two parts work normally, do not affect the regular job of circuit. Commonly used ESD protection parts of an apparatus has resistor, diode, bipolar canal of transistor, MOS, silicon controlled rectifier. Because MOS canal and CMOS craft compatibility are good, because this often uses MOS,tubal construction protects circuit.

 

The NMOS canal below CMOS craft condition has N-p-n of a transverse parasitism (source pole – P underlay – leakage pole) transistor, the transistor of this parasitism can absorb many electric current when open. The protective circuit that uses this one phenomenon to be able to design taller ESD compression to be worth inside lesser area, among them structure of the most typical parts of an apparatus is NMOS of grid ground connection (GGNMOS, gateGroundedNMOS) .

 

Below regular job circumstance, NMOS transverse transistor won’t guide. When ESD happening, the extinct area of leakage pole and underlay will produce an avalanche, electronic cavity is right also arise at the same time. The cavity that arises partly by the source extremely absorb, of the others had shed underlay. As a result of the existence of underlay resistor Rsub, make underlay voltage rises. When slanting with the PN knot between the source when underlay, the electron blasts off from the source enter underlay. These electrons are in between source leakage below the action of electric field, be quickened, produce the collision ionization of electron and cavity, form more electronic cavity to be opposite, make the electric current that has shed N-p-n transistor increases ceaselessly, make NMOS transistor produces puncture 2 times finally, right now puncture no longer reversible, bring about NMOS finally to provide damage.

 

To reduce output further the NMOS on drive is when ESD the voltage of two end, a resistance can be added between ESD protection parts of an apparatus and GGNMOS. This resistor cannot affect working signal, accordingly cannot too big. Polycrystalline silicon is used normally when drawing domain (Poly) resistor.

 

Use protection of one class ESD only, when big ESD electric current, the pipe of circuit interior is possible still by puncture. GGNMOS guides, because ESD electric current is very big, underlay and metal join on-line resistance cannot oversight, right now GGNMOS not can Qian live the voltage that inputs sink bar, what because let an input,the voltage of layer of silicon of sink bar oxidation achieves puncture voltage is the IR between GGNMOS and input sink underlay is pressed fall. To prevent this kind of situation, GGNMOS of a small size can be added to undertake 2 class ESD is protected around input sink, come with it Qian input sink bar voltage, following plan institute are shown.

 

The protective structure of common ESD and equivalent circuit

 

When drawing domain, must notice to protect 2 class ESD circuit to rely on closely to input sink, reach its in order to reduce the underlay between input sink and circuit of protection of 2 class ESD to join the resistance of the line. To be inside lesser area the picture gives the NMOS pipe of large size, draw it into finger in domain middling model, the should abide by I/O ESD strictly design when drawing domain is regular.

 

If PAD serves as output only, protective resistor and the NMOS that carry short ground connection did not need, the PMOS that its output class large size and itself of NMOS parts of an apparatus can act as ESD defends parts of an apparatus will use, average output level has double protection link, can produce latch in order to prevent so.

 

When the ESD structure of complete chip is designed, the attention follows the following principle:

 

(1) periphery VDD, VSS takes a line as far as possible wide, reduce on-line resistance;

 

(2) designs the voltage Qian between a kind of VDD-VSS structure, and VDD-VSS can be offerred when producing ESD passageway of release of electric current of direct low impedance. Bigger to the area circuit, had better be in of chip all around each set a such structure, if likely, the PAD of many VDD, VSS is placed in chip periphery, also can enhance integral circuit fight ESD ability;

 

(3) periphery protects what structural power source reachs the ground to walk along a line to take line departure with interior as far as possible, periphery ESD protects a structure to accomplish even design as far as possible, avoid domain to design occurrence ESD weak point;

 

(The design of structure of 4) ESD protection should be in if the influence with characteristic to circuit structure of area of the ESD function of circuit, chip, protection inputs ability of drive of speed of signal integrality, circuit, output to wait between undertake balancing a consideration, still need to consider the tolerance of craft, make circuit design achieves optimization;

 

(5) is in a few circuit that design actually, do not have direct VDD-VSS voltage Qian sometimes protective structure, right now, the voltage Qian between VDD-VSS reach release of ESD electric current to basically use complete chip the osculatory space of the trap of whole circuit and underlay. Want to increase the contact of trap and underlay more as far as possible in periphery circuit so, and the span of N+P+ is consistent. If have a space, had better reach by the PAD of VDD, VSS all around increase VDD-VSS voltage Qian protective structure, enhanced what VDD-VSS mode falls to fight ESD ability not only so, also enhanced what I/O-I/O mode falls to fight ESD ability.

 

Should have only commonly afore-mentioned roughly principle, below as eclectic as chip area consideration, general inferior of micron CMOS circuit fight ESD voltage to be able to achieve 2500V above, already OK and contented business refuses ESD demand with what circuit designs.

 

To deep inferior the design that micron exceeds large-scale CMOSIC need not groovy ESD protects ministry structure, mostly deep inferior the ESD structure that the Foundry product line of micron craft has him periphery level is offerred, the ESD structure that has strict level designs regulation to wait, it is OK that stylist needs to call its structure only, on the design of the respect such as the function that this can make chip stylist puts more energy in circuit itself, function.

 

4, last word

ESD protects a design as CMOS craft level rise and more and more difficult, the ESD protection that ESD protection has been input foot or output foot not simply designs an issue, however of complete chip electrostatic defend problem. Need to build corresponding ESD to protect circuit in circuit of each I/O in chip, in addition even from whole chip overall consideration, use whole (Whole-chip) defend the structure is a good choice, also can save the area of component of the ESD on I/OPAD.