The switch speed of transistor comes by its switch time namely token, switch time is shorter, switch rate is rapidder. The switch process bag of BJT is contained open and involve two processes, corresponding ground has open time Ton and close time Toff, the master switch time of transistor is Ton and Toff the sum.

 

How to raise the switch rate of transistor? —— can be designed from parts of an apparatus and use a technology two respects will try to consider.

 

(1) the switch time of transistor:

 

The switch weaveform of transistor is shown 1 times like the graph. Among them open process is divided again mix for defer rise two processes, close a process to be divided again to store and drop two processes, criterion total switch time shares transistor 4: Defer time Td, rise time Tr, memory time Ts and decay time Tf;

 

Ton=td+tr,  toff=ts+tf

 

When the influence of the additional electric capacity that causes in the place such as the envelope capacitance that takes no account of transistor, wiring capacitance, the switch time of transistor basically decides the structure of Yu Jiben body, material and use condition.

 

 

 

Td of ① defer time:

Defer time basically is the time constant that pair of emissive knots and capacitance of base of power of market report knot charge. Accordingly, decrease the main measure of short delay time, design from parts of an apparatus for, be like: The area that reduces emissive knot and market report tie (in order to reduce power base electric capacity) and reduce base the size of retrorse bias voltage (launch a knot in order to make can can enter as soon as possible slanting and open transistor) ; And use from transistor for, can increase the scope that inputs pulse of base electric current, in order to accelerate pair of knot capacitance charge speed (but if this base electric current is too big, will make transistor is in guide the saturated deepness after connecting increases, this can grow memory time again instead, so need is chosen appropriately) .

 

② rise time Tr:

Rise guide telling time is base the area is little child charge accumulates certain level, bring about transistor to reach critical saturation (although market report writtens guarantee 0 slant) when needs time. Accordingly, decrease the main measure of short rise time, from parts of an apparatus be like for the design: Of growth radical area little child life (in order to make little child accumulate accelerate) , reduce base area width and reduce knot area (in order to reduce critical saturation when base the area is little child charge is measured) , and the diagnostic frequency FT that raises transistor (in order to be in base the area is built as soon as possible certain little child chroma gradient, make collector electric current reachs saturation) ; And use from transistor for, can increase base to input the extent of voltaic pulse, in order to accelerate to base area infuse is little child speed (but base electric current also cannot pass big, will make store time is lengthened otherwise) .

 

Ts of ③ memory time:

Memory time is transistor from supersaturation condition (the condition that market report knot is slanting) quit critical and saturated position (market report writtens guarantee the 0 condition that slant) needs time, namely base the time that the excessive in area and market cable division stores charge disappears; . And these excessive are little child if the disappear owner of lost property of memory charge relies on compound action to finish, design from parts of an apparatus so for, the main measure that reduces short memory time is like: Wait in Au of mix into of market cable division those who will decrease division of short market cable is little child life (store charge is mixed in order to reduce the excess of market cable division quicken excessive memory charge disappear; But base the area is little child life cannot be decreased too shortly, can affect voltaic enlarge coefficient otherwise) , reduce denotative layer thickness as far as possible (in order to reduce the excessive memory charge of market cable division) . And use from transistor for, the main measure that reduces short memory time is like: The extent of pulse of base input electric current does not pass big (in order to avoid transistor saturation too deep, make excessive memory charge decreases) , increase base draw-out electric current (spend in order to accelerate the disappear stall of excessive memory charge) .

 

④ decay time Tf:

The process of the process of decay time and rise time happens contrary, it is a kind of process that the memory charge in allowing division of critical and saturated time base disappears gradually namely. Accordingly, to reduce short decay time, should reduce memory charge (reduce knot area, reduce base area width) and increase base draw-out electric current.

 

Anyhow, to reduce the switch time of short transistor, raise switch rate, besides try to consider on design of parts of an apparatus besides, the consideration that goes up to also can make as follows uses in transistor: A) increase base drive electric current, can reduce short delay time and rise time, but make store time increases somewhat; B) increase base draw-out electric current, can reduce short memory time and decay time.

 

 

 

(2) of transistor add fast capacitor:

When BJT introduces voltage drive, although reduce,receive outside base resistor and increase base retrorse voltage, can increase draw-out electric current, this stores to shortening time and decay time have certain profit. But, if resistor is received outside base too small, can increase the scope that inputs voltaic pulse, will make the saturated degree of parts of an apparatus is deepened and bring about memory time to lengthen instead; If base is retrorse voltage is too big, can make emissive knot slants instead again serious and increase defer time, so need has eclectic consideration in the round. Can infer, reduce short delay time and rise time to come through increasing base drive electric current while, the side effect that does not increase memory time and generation other again, if the graph shows the form of wave of a flight of stairs 2 times,weaveform of ideal base input electric current should be, input of such wave of a flight of stairs can overcome afore-mentioned contradiction, can achieve the goal that raises switch rate.

 

Actually, to realize weaveform of ideal base electric current, the base that if the graph is shown 3 times,can use conveniently inputs loop (differentiating circuit) , the as shunt-wound as base resistor RB CB in the graph is called add fast capacitor. One increases to add in base input loop fast after capacitor, although the voltaic weaveform of the input remains square wave, but through adding fast after the action of capacitor, weaveform of gets electric current of actual base input becomes very adjacent the base electric current at ideal is undee, can reduce short switch time then, raise switch rate.