[introduction] optimize power source to design in order to improve efficiency very important. Raise efficiency to be able to save the sources of energy not only, reduce generation of quantity of heat, return dimension of OK and narrow power supply. The article will discuss how to go up evenly tubal MOSFET (HS-FET) and the amount of MOSFET (LS-FET) leaving a valve are compared, in order to improve the efficiency that power source designs.

Graph 1 showed what have HS-FET and LS-FET to simplify circuit.

Graph 1: Have the circuit of HS-FET and LS-FET

When choosing MOSFET, how appropriate allocation the internal resistance of HS-FET and LS-FET in order to achieve optimal efficiency, this is a challenge to power source engineer.

The structure of MOSFET and loss are comprised

The choice of MOSFET concerns efficiency, design personnel need is conducted in its balance has between loss and switch loss. Conduct loss happening to be in during MOSFET is shut, because electric current has flowed to guide,cause; Switch loss occurs during MOSFET switch, do not have instant switch because of MOSFET and arise. These are caused by the capacitance behavior of structure of the semiconductor inside MOSFET.

MOSFET is a kind of collect shapes much component structure, become by paralell connection of structure of many MOSFET semiconductor. Shunt-wound MOSFET crystal is more, its guide electrify block (R_DS(ON)) smaller, but parasitism electric capacity is larger. Lesser R_DS(ON) Can reduce conduct loss, but can increase parasitism electric capacity, increase switch loss thereby. Accordingly, design personnel need acquires proper balance between resistor and capacitance.

Careful consideration needs when choosing MOSFET, but pass board the time that holds a test to decide to need overspend possibly and resource. Accordingly, build an accurate maths to the model will analyse loss and help MOSFET type selecting will more valuable.

Computation conducts loss

We understand relatively simple conduction above all loss calculation. Go out through the electric current of classics MOSFET and ripple electric current flowing to be able to be calculated inside individual cycle conduct loss.

To ensure accuracy, make need to consider R when this computation_DS(ON) With the relation between temperature. Because of the internal resistance R of MOSFET_DS(ON) Not be a fixed cost, it is met lift and increase as temperature.

If the graph is shown 2 times,conduct the computational method of loss. Among them I_O It is nominal electric current, Δ I_O It is voltaic ripple extent, T_J It is a knot lukewarm, k is temperature coefficient.

Graph 2: Conduct the computation of loss

Switch loss (parasitism effect)

The computation of switch loss is more difficult, the parasitism inductance that because need to consider every annulus way when computation,medium inductance causes, and what MOSFET falls in different voltage is nonlinear parasitism capacitance.

The graph shows the element of two kinds of parasitism that the consideration requires in be being calculated for switch loss 3 times.

Graph 3: Element of two kinds of parasitism

Switch loss (guide a loss)

Guide connect loss to include 3 level, following place narrate:

1.Level 1 (HS-FET phase) : Guide when HS-FET when connecting, leakage source voltage (V_DS) begin to drop, leakage source electric current rises all the time, till the V of HS-FET_DS(TOP) Voltage drop comes 0V, or HS-FET electric current (I_HS) rise to output electric current (I_OUT) .

2.Level 2 (regain level reversely) : During restoring reversely, I_TOP Reach peak value, next LS-FET begins to produce tension.

3.Level 3 (concussion phase) : When IHS stops wave motion, concussion ends.

Graph 4 showed with guide the switch loss with a relevant loss.

Graph 4: Guide a loss

Switch loss (involve loss)

Close loss to contain two level, following place narrate:

Level 1 (DS voltage rises) : I_DS As V_DS rise and drop. When I_DS Fall to 0A when, this phases ends.

Level 2 (oscillation) : When V_DS When stopping oscillation, this phases ends.

The graph is shown 5 times break loss to close.

Graph 5: Involve loss

Mathematical model and analytic test and verify

After all sorts of loss that realize circuit, can build mathematical model by following measure:

1.By demand setting circuit joins numerical value. According to above paragraphs medium formula reachs his nonlinear the value that parameter compensation cost will come to analyse MOSFET.

2.When transformer stable state is operated, run cycle of a switch at least, executive transient state is emulated.

3.Undertake integral to voltage and voltaic weaveform, the switch loss that gets MOSFET and conduct loss. This measure can pass power probe or mix electric current V_DS Undee photograph is multiplied will finish.

Once built a model, use the data that gets in the power loss that gets from above paragraphs, get efficiency is worth emulation, this value and circuit board (or data manual) in gotten efficiency curve undertakes comparative. If calculate,efficiency error is in 0.5% less than, think this model is accurate (see a picture 6) .

Graph 6: Mathematical model test and verify

Be based on mathematical tool to choose MOSFET

In the give typical examples of the article, we used total internal resistance to be 10 MOSFET of 100m Ω , according to afore-mentioned models computation is in not Alexandrine / the efficiency curve below rate of MOSFET leaving a valve. For example, 1:9rate is meant have a HS-FET (tall R_DS(ON), small electric capacity) with 9 LS-FET (low R_DS(ON), small electric capacity) .

Pass trade-off curve, we can conclude, the MOSFET optimal rate that 12V uses to 3.3V, 10A is 3:7(see a picture 7) . Curve of this group of efficiency makes clear, although the amount of MOSFET is same, different rate also will bring about different efficiency curve. From this the optimal MOSFET rate that we can find best efficiency curve to fall.

Graph 7: Optimal MOSFET rate

Graph 8 showed in identical input and output norms and identical output electric current falls, if where,different MOSFET finds the smallest loss in circuit to nod below rate. Design personnel must remember these standards well when choosing MOSFET rate.

Graph 8: The comparison of optimal efficiency

Closely related the choice of epilogue MOSFET and circuit efficiency, and mathematical mathematical model can simplify the choice of MOSFET transistor and design. Want to obtain mathematical model, need considers the parasitism parameter of circuit, use efficiency curve to come result of test and verify. The article introduced how to build a model to choose appropriate HS-FET and LS-FET rate through accurate maths, achieve efficiency of best power source thereby. If need to know more news, consult please the MOSFET driver of MPS and power source solution.

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