[introduction] in involve radio frequency (in the hardware test of RF) , the choice can be configured, already the reliable signal source of calibration is among them one of the most important facets. The article offerred the height that is based on Raspberry Pi compositive solution, its can be used at synthesizing RF signal generator, output DC comes the onefold frequency signal of 5.5 GHz, output power limits comes for 0 DBm – 40 DBm. The system that offers is based on direct figure frequency to synthesize (DDS) framework, outputted power and frequency character to undertake calibration to its, can ensure in limits of whole job frequency, output power maintains the less than of ± 0.5 DB that requires power level in place.

Brief introduction

RF signal generator, especially the RF signal generator of microwave frequency, it is to be based on Suo Xianghuan normally previously (PLL) frequency synthesizer 1 come compose is built. PLL support consults from low frequency signal generates stable high frequency signal. Graph 1 showed model of a basic PLL. This model by feedback system (include to include a voltage to control an oscillator among them (VCO) use at the change to output frequency) , error detector (use at inputting referenced frequency and output frequency quite) and scale down implement composition. When scale down implement output frequency and phasic the frequency that is equal to input reference and phasic when, annulus road is thought to be in a lock to decide position. ^{2 – 5}

Graph 1. Basic PLL model

What the basis applies is different, DDS framework may compare PLL to offer a kind of better replacement scheme as frequency synthesizer. . Graph the 2 is based on DDS signal generators that showed a pattern. Harmonious word applies at phasic accumulator, output the slope of brae certainly by latter. The perch of accumulator passes extent sine converter, arrive at DAC finally. Compare with PLL photograph, the framework of DDS has clear advantage. For example, phasic accumulator can implement DDS number more harmonious than be based on the output frequency with the frequency more careful synthesizer of PLL resolution.

Graph 2. Be based on the typical signal generator of DDS

PLL switch time is the between function when set-up time and VCO answer way of its feedback annulus, as a result of the limitation of oneself property, its rate is slower, and the restriction that DDS accepts delay of several word processing only, because this has rapidder switch rate. Be in respect of circuit board measure, the area of DDS is smaller, facilitating system is designed, a lot of hardware RF design difficult problem also be readily solved 6.

Below one part will discuss CN0511. A complete DC that is based on DDS framework is designed to the overall system of signal generator of wave of 5.5 GHz sine. Reach framework of discussion vector signal generator its norms next. Debate the focal point systematic clock after that, include clock to consult the circuit between requirement and clock management unit and vector signal generator joins. Also can involve power source framework and systematic distribution, how does system of whole of farther specification achieve high power efficiency and come loose reasonably hot property. Subsequently ” software framework and calibration ” part will be controlled around systematic software and calibration spreads out discuss. The quick control that this part will explain to software is offerred and how calibration outputs power. Last part will show integral system performance, include a system the hot property of power of output of phasic noise, calibration and system.

Systematic level framework and design think

A: Systematic level is designed

The graph shows a system 3 times is the complete DC that is based on DDS framework to signal generator of wave of 5.5 GHz sine. Core of four switch DAC and compositive output amplifier are offerred inside limits of whole job frequency extremely low lack fidelity, the output that deserves to have 50 Ω matchs terminal.

Board carry clock solution to include referenced oscillator and PLL, consequently need not exterior clock source. All power source all come from Raspberry Pi to make the same score bedplate, its have freeboard power source to restrain than (PSRR) manostat and function of passive filter wave, can make reduce the effect of power source converter to RF function considerably.

Graph 3.CN0511: The frequency that is based on RPI synthesizes RF signal generator

Graph 4. What use vector signal generator (the functional-block diagram of AD9166)

Graph 5.ADF4372 RF8x outputs class

The graph shows a framework 3 times to be able to be used at all sorts of application such as signal generator of radar, automatic test, aleatoric undee generator and only news. And only news signal generator came true to apply in the article. The following bar will discuss the main part that CN0511 includes to become parts of an apparatus.

B: Vector signal generator

If the graph is shown 4 times, uses DC includes a 6 GSPS to signal generator of 9 GHz vector (1 times do not clear mode) interface of data of DAC, 8 passageways, 12.5 Gbps JESD204B and have oscillator of many numerical control (the DDS of NCO) . At the same time this parts of an apparatus is the digital data method that height can deploy, include interpolation filter, turn over SINC compensation and digital first detector, support flexible spectrum program.

48 when the graph shows a system 4 times to use DAC but NCO of process designing modulus with very tall precision (resolution of frequency of Hz of 43 μ ) the digital frequency that realized signal moves. The NCO of this DAC needs SPI to write interface speed to achieve 100 MHz to be able to update frequency tuning word quickly only (FTW) . SPI still supports configuration and monitoring all sorts of function module in this DAC. This design did not use JESD channel, parts of an apparatus is used below NCO mode only.

Graph 4 medium vector signal generators are compositive the output RF amplifier that Ω of Chan Duan, 50 matchs, because this need not use interface of complex RF output circuit. Express the 1 main norms that showed AD9166 and the function below all sorts of conditions.

Express 1.AD9166 main norms

 

C: Systematic clock

Graph 2 medium systems used ADF4372 PLL (see a picture 5) , this is the broadband frequency synthesizer of a compositive VCO, when be used together with filter of exterior annulus road and exterior and referenced frequency, can regard decimal N scale down or frequency of integral N scale down as synthesizer. In addition, VCO frequency can undertake 1, 2, 4, 8, 16, 32 or 64 scale down, because this user can be in RF8x generation is low output frequency to the RF of 62.5 MHz.

The quality of clock source (exemple if is phasic noise and stray character) and its and the interface that clock of high speed DAC inputs, can immediate impact communicates function. Accordingly, phasic noise and other spectrum content will be arrived to output by direct modulation on signal. To achieve optimal and integral attrib border stray and phasic noise performance, ADF4372 used sheet to carry reference to input signal, next the clock that its times frequency uses at high speed DAC with generation, if pursue,6 are shown.

The circuit between graph 6.ADF4372 and AD9166 joins

D: Power source framework

If the graph is shown 7 times,the systematic power source of CN0511 is cultivated, be based on systematic load to ask its efficiency rises 90% , used LTM8045, LTM4622 and ADP5073 switch manostat respectively, . Choose the low pressure such as ADM7150, ADM7154 and ADP1761 to differ linear manostat (LDO) will be DAC, amplifier, PLL and VCO power supply, its have exceed low noise and tall PSRR performance, can achieve performance of optimal and phasic noise.

LTC2928 of controller of sequential of use power source will ensure high speed DAC presses correct and ordinal electrify, prevent damage its interior circuit. IC can monitor controller of sequential of this power source and run 4 voltage course, have the electrify time that dominates each voltage course and other monitoring function, include to owe among them press and control monitoring and report function too.

E: Layout consideration

Extremely high-powered to this kind of need the application with higher output frequency, PCB (printed circuit board) the choice of material can have very big effect to the result. Graph 8 showed commendatory CN0511 PCB folds a layer, it uses data of Rogers 4350 dielectric on the layer that includes RF to take a line, the signal attenuation of 3GHz above decreases on the oldest rate, ensure in RF output part obtains first-rate signal integrality.

Graph 7. Systematic power source is cultivated

Graph 8. Commendatory PCB cross section and fold a layer

Hot property and PCB design and working environment are direct and relevant. Come loose for what improvement designs hot property, come loose in PCB hot solder dish on hit medicinal powder hot via.

Software framework and calibration

A: Software control

Hope to be able to control instrument device neatly easily in any application that involve a signal generator. Because it needs to contain a piece the SD card of Kuiper Linux mirror to insert Raspberry Pi only, can think CN0511 is Plug and Play consequently. Kuiper Linux mirror includes all and necessary software that place of control signal generator wants. Two kinds of methods output power and frequency convertibly: Use PyADI-IIO module writes code, or user interface of use IIO-Oscilloscope graph (the output that GUI) input needs.

PyADI-IIO is the Python abstract module of ADI hardware, contain industry to input / output (IIO) driver. This module offerred the Python method that uses easily simply and property to control hardware. Through very simple Python code travel can control this board, these code can be in this locality or move remotely. Can use simple For to found any frequency scanning circularly with a few defer, use at testing other equipment.

IIO-Oscilloscope is one crosses platform GUI to use a program, need user input outputs power extent and frequency to serve as parameter.

These two module all offer PyADI-IIO and IIO-Oscilloscope the output of finish lukewarm sensor: One is inside PLL IC, another is inside IC of vector signal generator. Graph 9 revealed these two software module and with CN0511 board the other component that communication place wants (LibAD9166, LibIIO and Linux kernel) . Graph 9 in indication LibAD9166 is another library that assembles beforehand on Kuiper mirror, use at accurate control to output power, include the C++ code that place of output calibration power requires, specific use at this board. Will be in about how realizing the theory of calibration B section: Output continues to discuss in power calibration.

Graph 9. The software package block diagram that needs through PyADI-IIO and IIO-Oscilloscope and equipment communication place

B: Output power calibration

In signal generator application, frequency band evenness is spent is a crucial parameter. In this system, the relation character that outputs power and frequency is main decide by the output of vector signal generator. Rise as frequency, output impedance sheds a value to begin to reduce continuously from its. Any impedance of this kind of change that outputs impedance and laden place are broken deserve to be met immediate impact outputs power. In addition, the Sinc that can forecast rolls the frequency that falls to also can affect output power to answer. Graph 10 discuss and showed those who measure not the relation of calibration output power and frequency. To overcome these adverse elements, we undertook software calibration to outputting the relation of power and frequency.

The knob that uses at corrective output power included two register of AD9166: The 10 register Ioutfs_reg that sets full span electric current (address 0x42 and 0x41) the 16 register Iout_reg with electric current of setting full span (address 0x14E and 0x14F) . These two register are in charge of controlling the output electric current of AD9166 DAC, the input that this also is AD9166 amplifier (graph 3) .

Ioutfs_reg is offerred about the limits of output power trends of 10 DBm, this is the good value that uses 10 at adjusting a figure to show needless character.

Graph 10. Output the relation of power and frequency: Not the output power of calibration

From measure a result to look, every PCB print shows the same figure character that the graph shows 10 times, it is deflection existence difference only. Considering this, we developed Cheng of two calibration exemple. Program of the first calibration needs to be carried out only, with the parameter that at getting calibration whole appearance place needs, make its evenness is changed, ; The 2nd program is used at corrective and different board the deflection error between, serve as every board manufacturing test moves. Cheng of two calibration exemple all is measured through output, calculate and be based on calculative register to adjust will finish.

If the main design train of thought of Cheng of exemple of the first calibration pursues 11 are shown. Above all, graph 10 medium whole and characteristic curves are divided into many frequency interval, these interval can be used express approximately from Fmin[x] to the line segment of Fmax[x] , among them the index that X is interval, x ∈ [0, 31] , and X is integral. Actual design chose 31 interval, but for better illustrate, 3 interval showed only in graph 11a. To every interval, need obtains two constant: One is to be used at the Offset_correction with corrective deflection (graph 11b) ; One is to be used at the Gain_correction with corrective gain (graph 11c) . Still need memory parameter F_Min[X] in order to dog interval.

Graph 11. The visible citing of calibration exemple Cheng: (A) divides characteristic curve into many parts; (B) is corrective to undertaking deflection every partly; (C) is corrective to undertaking slope every partly.

The flow chart of code of working principle bogus that graph 12a is Cheng of exemple of the first calibration. To finish this algorithm, need uses very accurate spectrum analyzer to measure output power (use Keysight E5052B/R&S FSUP) . Cheng of the first exemple (graph 12a) the parameter of generation is used at Cheng of exemple of the 2nd calibration, if pursue,12b place is shown.

Graph 12. Bogus code flow chart: (The Cheng of exemple of the first calibration that A) runs only; (B) is in every CN0511 board on the Cheng of exemple of the 2nd calibration that move.

Cheng of exemple of the 2nd calibration (graph 12b) be in the light of every PCB in producing a test print moves, the Offset_correction parameter that is every interval increases same constant. When Cheng of the 2nd exemple ends, to every interval, modification parameter Offset_correction[x] , Gain_correction[x] and F_Min[X] is memory in the EEPROM of circuit board. Become when circuit board works, these parameter will be used further in software.

Output power to install calibration, software uses formula 1 will calculate the outputs power Ioutfs_reg register that adjusts frequency Fx place is worth, with. Fx is the frequency inside interval X: Fx ∈ [F_Min[X] , F_Max[X]) , fx is true positive number, F_Min[X] is the smallest frequency of the interval that index is X.

If formula is shown 1 times, memory of every X interval must is on circuit board 3 parameter, so that undertake outputting corrective: Namely Offset_correction[x] , Gain_correction[x] and F_Min[X] .

Systematic performance

A: Calibration outputs power

Graph 13 showed CN0511 differs in a few kinds the broadband below output power level compensates frequency band evenness to spend. Mix in 0 DBm to the setting – any output power between 40 DBm, it is ± 0.5 DBm to the precision inside the whole frequency band of 5.5 GHz from DC.

Graph 13. Calibration outputs the relation of power and frequency

B: Phasic noise

The quality of clock source and the interface of its and end of AD9166 clock input can affect phasic noise performance directly. Can be turned be output signal directly in the phasic noise that specifies frequency deflection part and stray. Graph the 14 unilateral that showed the course is measured are taken (SSB) is phasic the relation of noise and frequency deflection. All data are collected below the circumstance that is full span in output power setting. Use board carry 122.88 MHz CMOS to press accuse crystal oscillator to use as systematic clock is referenced.

Graph 14. The system is phasic noise function

C: Heat up function

According to application and configuration, the power comsumption of high speed DAC may be close to 4 W. This parts of an apparatus uses bare chip to enclose will reduce thermal resistance and allow chip to come loose directly hot. Use the mechanical radiator that brings fan to send out enclosed quantity of heat. Below the circumstance that installs radiator, the highest temperature reading that LTM4622 shows below the environmental temperature of 25 ° C is 60.6 ° C about.

Conclusion

The article offerred the signal source of a kind of high frequency, low lack fidelity, low noise. The system of place introduction is a kind of low cost RF that uses the DDS framework that is based on high speed DAC solution of signal frequency synthesizer, through using the vector signal generator that is based on DDS technology, this system than simple PLL have multinomial advantage, for example tuning of simplification, low lack fidelity, high resolution, close to instantaneous jump frequency, phasic with extent modulation.

The multinomial advantage of DDS framework makes adjust and calibration output power and frequency of fine tuning output become a possibility. Calibration exemple Cheng is added to be able to be offerred for the user in the system consult to the output of 5.5 GHz from DC signal sound, precision is ± 0.5 DBm, dynamic limits arrives for 0 DBm – 40 DBm. To lab instrument, this is a kind of approximately good solution.

Express one’s thanks to

Thank place to have the ADI engineer that provides precious technology support for the article.

Referenced circuit

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²Mike Curtin and Paul O ‘ Brien. “The lock photograph annulus that is used at high frequency receiver and emitter ” . ” imitate speaks ” , the 33rd the 3rd period, in July 1999.

³VCO design manual. Mini-Circuits Corporation, 1996.

⁴Leon W. Couch. Number and imitate communication system. Macmillan Publishing Company, 1990.

⁵Peter Vizmuller. Radio frequency designs a guideline. Artech House, 1995.

⁶Jim Surber and Leo McHugh. “Odd chip is direct digital frequency synthesis and imitate PLL ” . ” imitate speaks ” , the 30th the 3rd period, in July 1996.

EVAL-CN0511-RPIZ user guideline. ADI company, in January 2023.

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