[introduction] modulus converter (signal of ADC) general imitate — namely the concrete signal such as temperature, pressure, voltage, electric current, distance or luminous intensity — the number that changeover is this signal shows. Next, the system is OK processing, control, computation, transmit or store this number shows.
This experimental activity aims to build demonstrative sex give typical examples to discuss the idea that modulus changes through compose.
Modulus converter (signal of ADC) general imitate — namely the concrete signal such as temperature, pressure, voltage, electric current, distance or luminous intensity — the number that changeover is this signal shows. Next, the system is OK processing, control, computation, transmit or store this number shows.
Graph 1. Modulus changeover
ADC undertakes sampling to imitate weaveform with even time-interval, assign digital value every example. Digital value codes with the binary system the format output end in converter shows. Divide through inputting sampling imitate voltage with fiducial voltage, multiply again get this value with digital yardage. The resolution of converter comes by the binary digit number in outputting a code set.
Graph 2. The number outputs a code
ADC carries out two processes: Sampling and quantify. ADC represents the imitate signal of infinite resolution to the number that is finite resolution is piled up. ADC can produce 2N digital value, among them N states the binary system outputs digit. Because the resolution of converter is finite, imitate input signal will fall in quantify n between, cause inherent uncertainty thereby or quantify an error. This error can define the biggest dynamic scope of converter.
Graph 3. Quantify a process
Sampling process provides signal of successive time domain, signal value is measured with disperse, even time-interval. Pass this course, according to Nai Kui this special the biggest bandwidth that criterion can decide sampling signal. This theory thinks, signal frequency must is less than or be equal to half sampling frequency to be mixed in case fold. Mix folding is to point to through sampling process, the circumstance of the frequency signal outside needing signal frequency Duan Zhi appears inside target bandwidth. Nevertheless, in communication system design, can use this to mix fold a process to be down high frequency signal changeover to be low frequency signal. This owes sampling technology namely. The standard that owes sampling is ADC has enough input bandwidth and dynamic limits will collect signal of top end frequency.
Graph 4. Sampling process
Sampling and quantifying is main idea, because they defined the function limit of ideal ADC. In an ideal ADC, code transition is apropos apart 1 LSB (lowest is effective) . Accordingly, to a N ADC, mutual 2N digital code, and 1 LSB = FS/2N, among them FS inputs voltage for full span imitate. However, actual ADC operation also is not the influence of ideal effect, the error that produces exceeded the error of converter resolution and decision of sampling rate place. The metropolis in a lot of communication related to ADC and dc performance standards reflects these errors.
Graph 5. The changeover function of ideal ADC
Inside this limits, any imitate inputs can produce same number to output a code.
● ADALM2000 learns module actively
● The breadboard that do not have solder and jump the line is covered
● Amplifier of an OP482 operation
● Converter of frequency of two AD654 voltage
● Resistor of Ω of 3 1 K
● Resistor of Ω of 5 10 K
● Capacitance of a 1 NF
● A SN74HC08 and door
● A SN74HC32 or door
● Inverter of a SN74HC04
● Capacitance of F of μ of a 1
● An AD7920 12 ADC
Shine put ADC
Flash ADC, also call collateral ADC, it is one of the swiftest methods that change imitate signal signal of amount to word. Flash ADC suits to need the application of extremely wide bandwidth very much, but its power comsumption is taller than other ADC framework and normally limitation is 8 resolution. Typical give typical examples includes data to collect, oscillograph of processing of satellite communications, radar, sampling and driver of high density hard disk.
Flash ADC by high speed comparator cascade and into. To a N converter, circuit uses 2N -1 comparator, have 2N at the same time resistor offers fiducial voltage. When the fiducial voltage that when the imitate of comparator place of input voltage prep above brings to bear on, its are outputted 1. Otherwise, comparator is outputted 0. Code from 1 turn into the dot of 0 inputs signal to be less than corresponding comparator namely the dot of fiducial voltage n.
See the circuit that the graph shows 6 times please.
Graph 6.Flash ADC, imitate side circuit
This circuit shows the imitate side of 2 Flash ADC, its framework calls thermometric code (a yuan of code) encode. To this kind of circuit, need uses additional logistic circuit to pile up a yuan decipher to output a code into appropriate number. Through using logic and door, or the door and blame door, we are OK compose is built have coder only. Its output the binary system that is original numerical value to express, highest and effective input from 0 begin.
Graph 7.Flash ADC, encode output
Breadboard of graph 8.Flash ADC joins
The place before be like is narrated, flash ADC uses high speed comparator to compose is built and be become, but for convenient for the purpose of, we will use OP482 amplifier of 4 passageways operation will introduce working principle. Or, can use 4 AD8561 comparator to come compose builds this circuit.
On the breadboard that do not have solder compose builds the circuit that the graph shows 7 times. This is a circuit of 2 Flash ADC that are used at having encode to output.
Offer voltage of power source of ± 5 V to circuit. In the AWG1 of signal generator of Scopy lieutenant general configuration is those who have deflection of extent of peak value of 5 V peak, 2.5 V and 100 Hz frequency to rise brae is toothed wave. Use AWG2 at offerring 5 V for ADC constant and fiducial voltage.
Configure logistic analyzer, make the passageway group that digital passageway DIO0, DIO1 and DIO2 form to pile up decipher in the light of a yuan, passageway DIO6 and DIO7 form a passageway group that is aimed at collateral output decipher.
If the graph is shown 9 times,output signal weaveform.
Graph 9.Flash ADC, output a code
Passageway of a yuan of group expresses the output thermometer code of 2 Flash ADC, through be in whole and usable limits (the output value that 0 V offers all possibilities to voltage of imitate of input of the change inside 5 V) . Collateral passageway states the binary system that is equivalent to ADC outputting condition is worth.
Voltage frequency converter uses as ADC
In this special application, converter of AD654 voltage frequency uses as ADC.
Graph 10. Voltage frequency converter uses as ADC
To realize changeover, should join the output end of converter compositive and removed timer / the microcomputer of incident tally.
The signal edge during computation (rise or drop) total count and input voltage become direct ratio. Here specific setting falls, 1 V full span inputs voltage to be able to generate 100 KHz signal. If computation cycle is 100 Ms, total count will is 10, 000. Can input voltage certainly according to the scale with this maximum next. Accordingly, computation is 5000 when, corresponding input voltage is 0.5 V.
Compose builds breadboard circuit with using voltage frequency converter as ADC, if pursue,11 are shown.
Offer voltage of 5 V power source to circuit. the AWG1 of the signal generator configuration is 1 V constant voltage.
Configuration oscillograph, make passageway 1 on indication output signal, and from the passageway 1 ” measure ” option Ka Zhongqi is measured with frequency. If the graph is shown 12 times,output signal weaveform.
Graph 11. Voltage frequency converter uses as ADC, breadboard join
Graph 12. Converter of frequency of the voltage below voltage of full span input uses as ADC
Graph the output signal when 12 medium curves showed voltage frequency converter uses 1 V full span to input voltage is undee. Ask an attention, corresponding output frequency is 100 KHz.
the input voltage setting is 0.5 V now. If the graph is shown 13 times,output signal weaveform.
Graph 13. Converter of frequency of the voltage below voltage of half span input uses as ADC
The output signal when showing voltage frequency converter uses half span of 0.5 V to input voltage in the graph is undee. Ask an attention, output frequency is 50 KHz now.
Successive approachs register (SAR) ADC
Successive approachs register (SAR) ADC is in when be being changed every time, quantify n likely in the light of place, through the binary system the search drafts progressive die undee changeover to express for disperse number, gather together to be outputted for the number finally.
Normally, SAR ADC circuit comprises by 4 stature circuit:
● Use at collecting input voltage (VIN) sampling maintains circuit (S/H) .
● Imitate voltage comparator, it VINUndertake comparative with the output of in-house DAC and will output as a result quite to SAR.
● SAR child circuit, use at offerring the similar number of VIN to pile up to in-house DAC.
● In-house and fiducial DAC, offer the imitate voltage that is equivalent to SAR number piling up output to comparator.
The typical framework of graph 14.SAR ADC
Undertake initialization to SAR, make highest and effective (MSB) is equal to a number 1. Input this code DAC, next the imitate equivalent signal that DAC piles up this number (VREF/2) supplies comparator circuit, so that input voltage with sampling,undertake comparative. If this imitate voltage exceeds VIN, criterion comparator makes SAR replacement this; Otherwise, this is reservation 1. It is a setting the 1 test with hand-in-hand same travel next, carry out this binary system to search continuously till SAR medium every had checked too. Gets code is the digital approximation of sampling input voltage, end finally in changeover by SAR (the output when EOC) .
Graph give typical examples of 15.4 SAR ADC
Graph a 15 give a demonstration that showed 4 changeover. Y axis states DAC outputs voltage. Give typical examples is here medium, show V quite for the first timeIN <VDAC. Accordingly, 3 settings are 0. It is DAC setting next 0100 hand-in-hand travel is compared the 2nd times. As a result of VIN >VDAC, 2 maintain for 1. It is DAC setting next 0110 hand-in-hand travel is compared the 3rd times. Will 1 setting is 0, it is DAC setting next 0101 undertake be comparatived finally. Finally, as a result of VIN >VDAC, 0 maintain for 1.
Show the working principle of SAR ADC to use ADALM2000 key, will use to DAC parts of an apparatus in the circuit that discusses in the experiment next time, but this setting lieutenant general uses 4 DAC (is not 8) . The output end of DAC will receive comparator repeatedly, undertake emulation to SAR through script at the same time, the output that this script is based on comparator carries out a binary system to search and create true binary value.
Principle of graph 16.SAR ADC pursues
Compose builds the breadboard circuit of SAR ADC, if pursue,17 are shown.
Breadboard of graph 17.SAR ADC joins
Use two accurate track in OP484 integrated circuit at this SAR ADC to course operation amplifier, one is used at R-2R echelon DAC, another is outputted as DAC and input the comparator between voltage.
Offer voltage of power source of ± 5 V to circuit. Configuration oscillograph,
Make passageway 1 on indication comparator outputs signal, passageway 2 on indication DAC outputs signal.
The passageway of before 4 numbers in will logistic analyzer in group, it is decoder setting collateral.
Download SAR ADC script, use Scopy interface to run scenario.
Use trial and error, the feedback that receives according to outputting end from comparator updates a number to pile up.
Use oscillograph to realize what DAC outputs to approach behavior inside time domain visible. The weaveform of generation is shown 18 times like the graph.
Successive of graph 18.SAR ADC approachs weaveform
After approaching measure through a few, output value is close to an input to be worth (the setting is 2 V) .
AD7920 12 ADC
AD7920 is SAR ADC of a 12 high speed, low power comsumption. It can use power supply of only power source, limits of power source voltage comes for 2.35 V 5.25 V. This ADC supports serial port. Serial clock offers changeover clock, control the information that comes from AD7920 to transmit during changeover. Transition and data collect a process to pass / CS and serial clock undertake controlling, created a condition for parts of an apparatus and microprocessor or DSP interface thereby. Input signal is in / the fall of CS the edge undertakes sampling, and changeover at the same time herein is started. Graph 19 those who showed ADC sampling phase and changeover level simplify principle sketch map.
In sampling phase, SW2 closes and SW1 park A. Here the setting falls, comparator maintains in balance position, sampling capacitance collects the signal of VIN. To make ADC starts transition, SW2 disconnects, and SW1 moves to positional B, make comparator becomes lopsided. Repartition DAC can add control logic and charge to mix the fixed charge amount in subtractive sampling capacitance, make comparator restores to balance position, change then finish.
Graph 21 gave out the typical join setting of AD7920. VREF is taken from in-house VDD, accordingly its should solve Ou adequately. This will offer 0 V to input limits to the imitate of VDD. Changeover is outputted with 16 words as a result, before 4 for 0, hind 12 or 10 MSB are a result.
Graph 19.AD7920 sampling and changeover phase
Graph 20.AD7920 breadboard joins
Graph 21.AD7920 model joins
Open Scopy, make can positive electricity source is 3 V. The passageway that configures a signal generator 1 arrive for 0 V the some between 3 V is constant value, for example the intermediate value 1.5 V of this region. Can monitor on oscillograph the real value of these voltage.
Graph 22.VIN(passageway 1) with VREF(passageway 2) voltage
In logistic analyzer, it is DIO0, DIO1 and DIO2 configuration passageway of a group. this groups of passageways the setting is SPI, the SPI signal that each passageway setting is correspondence — DIO0 is CS# , DIO1 is CLK, DIO2 is MISO. When CS# drops to be transmitted along the data that start, should be DIO0 trigger setting drop along. DIO1 trigger the setting is low n, install a lieutenant general from trigger ” trigger is logistic ” the setting is AND. DIO2 is the output signal of ADC, do not need trigger setting. Make can logistic analyzer, it is waiting to spark signal.
Clock signal is configured in mode generator. Make can DIO1 passageway, its ” mode ” the clock that the setting is 5 MHz frequency, click Run next (move) . Can control CS# from digital IO tool. When the DIO0 that cites a base for output when switch configuration cites a base, changeover opportunity begins. If the fall of CS# the low n condition of edge and CLK is coinstantaneous, changeover will be started, should see in logistic analyzer output signal and MISO are hexadecimal data, if pursue,23 are shown.
The SPI of graph 23.AD7920 is received
The formula that can use ADC to change function checks a result, among them word of MISO data amount to outputs a code, oscillograph passageway 1 on read extraction voltage to be imitate input, oscillograph passageway 2 on read extraction voltage to be fiducial input, n is the digit of AD7920.
The result that above computation reachs is ADC inputs voltage to be 1.5 V, in oscillograph passageway 1 go up those who numerate also is this value.
Additional activity: Double slope ADC
Double slope ADC (or aberrant) the core parts of an apparatus that is volmeter of a lot of high accuracy number. This framework has a few useful character: Because most error source can offset, because this needs a few nice element only, still can restrain specific noise frequency through configuration, be like 50 Hz or noise of 60 Hz circuitry, and be opposite high frequency noise is not sensitive.
Graph 24. Structure of double slope ADC
The working principle of converter is as follows: Bring to bear on to integrator inside fixed time sealed input voltage (call uphill (Runup) ) , bring to bear on to integrator next as contrary as input polarity foregone and fiducial voltage (call declivous (Rundown) ) . Accordingly, input voltage can mix according to fiducial voltage declivous – uphill time gets than computation:
Graph 25. Integrator of double slope ADC outputs weaveform
Can see, the precision of double slope converter does not suffer the effect of most component tolerance:
● The resistor of integrator and capacitance tolerance can affect output slope, but also can affect at the same time mix uphill declivous.
● Be being used at installing uphill time and the time base error that measure declivous time is identical to the influence of two time.
Fiducial voltage must accurate, because it is met,immediate impact measures an outcome. Another error source is the dielectric in integrator capacitance is absorbed, because this polypropylene or polystyrene are good choice, and aluminium electroanalysises not quite appropriate.
Graph 26. Integrator of double slope ADC outputs weaveform
The graph shows the frequency that is double slope ADC 26 times to answer. Time-interval is decided in solid (uphill) inside to inputting sampling, uphill the voltage when the voltage influence to the result and uphill end is right in the begining the effect of the result is same. Also call this box type average sometimes, it can restrain the interference that happens below the frequency such as 1/T, 2/T, 3/T (noise) . The 50 Hz noise at 10 cycle mixes correspondence of 200 Ms integral time 12 periodic 60 Hz noise; Because it can restrain circuit noise, because this regards uphill time as its normally.
Open the LTspice that here offers? File DualSlope.asc.
Graph 27. Principle of integrator of double slope ADC pursues
Move emulate, exploration Vintegrate node.
Graph 28. Integrator of double slope ADC is emulated 1
Should emulate in adding noise of 60 Hz circuitry dc to input voltage. Through.step the instruction runs a few kinds of conditions — a few of voltage of input of 1 V, 2 V, 3 V, 4 V 5 V and noise of 60 Hz circuitry different and phasic. Because 200 Ms is uphill time is cycle of 60 Hz circuitry is integral, so noise is answered in frequency in for 0, and no matter phasic how, declivous time is insusceptible. Change frequency for 62.5 Hz, make its are in the peak value that frequency answers.
Graph 29. Integrator of double slope ADC is emulated 2
Build breadboard circuit for compose of double slope ADC, if the graph is shown 30 times, have link to M2K according to graphic representation.
Graph 30. Circuit of breadboard of integrator of double slope ADC
Open Scopy. Dual_slope_scopy_setup.ini of file of kernel Scopy initialization is installed with the help.
Power source: Make can dog, the setting is ± 5 V.
Digital IO: DIO2 setting is OUT, the setting is 1.
Mode generator: Group DIO0, DIO1, mode: Guide (Dual_slope_pattern.csv of to load file) . Frequency setting is 5 Hz.
Signal generator: 1 initiative setting is the passageway constant 2.5 V.
Oscillograph: 200 Ms time base, 1 setting is the passageway 400 MV/ scale. Drop edge trigger, 200 MV (will spark in the begining in integrator replacement interval M2K) .
Graph 31. Integrator of double slope ADC is undee
Receive repeatedly when fiducial voltage source – when 5 V power source will input voltage setting to be 2.5 V, notice please declivous for 2 case (400 Ms) , and it is 1 case uphill (200 Ms) . Accordingly:
VIN × of = 5 V (200 Ms / 400 Ms) = 2.5 V
Input voltage through the change, can see uphill time produces change. Weaveform is shown 32 times like the graph.
Graph 32. The integrator of double slope ADC of different input voltage is undee
When realizing double slope converter actually, will use a small controller to control integrator and be installed uphill / measure declivous time. Most small controller offers tally peripheral, come true very easily consequently.
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