Of transistor small shrink problem

Of transistor small shrink problem

[introduction] in semiconductor industry, “ is small shrink (Scaling) ” is a term that often appears, say for example, we often hear concerned transistor in the news of semiconductor industry small shrink (namely accept rice class (Nano-scale) measure is narrow to atomic level) information.
 
In semiconductor industry, “ is small shrink (Scaling) ” is a term that often appears, say for example, we often hear concerned transistor in the news of semiconductor industry small shrink (namely accept rice class (Nano-scale) measure is narrow to atomic level) information. Or, we ever had heard of again, because the electronic equipment such as the smartphone that we use daily used a capacity bigger (Scaling) memory semiconductor, because this can store the video with higher definition. The news of whatever appearance, mean basically small shrink (Scaling) progress.
 
Above these progress are by component interface is accumulated (Footprint) of contractible, three-dimensional structure expand, new material and the use place to bring effect that innovate a structure. The digital age nowadays because the development of these technologies mixes above to progress and be able to hold water. Nowadays, as a result of,the electronic equipment that makes our daily life produces world-shaking to change is small shrink (Scaling) and be able to be born, and, today’s we need to use the digital information that uses finger to be able to obtain magnanimity only.
 
Of transistor small shrink (Scaling)
With respect to semiconductor small shrink (Scaling) , rub Er law is well-known. Become namely when the price is changeless, the amount every other of yuan of parts of an apparatus that can accommodate on integrated circuit 18 – 24 months can increase one times, function also will promote one times.
 
Come a few years recently, as photoetching (Lithography, the processing technique that becomes circuit pattern in photocopy of brilliant round face) etch with plasma (Plasma Etching) technical progress, semiconductor industry is narrowing stage by stage transistor this one important (perhaps saying is indispensable) make element, and achieved greater progress.
 
In addition, the technical node with respect to semiconductor (Technology Node) , the brake that what point to commonly is transistor extremely (the length of Gate) . Say for example, what the technical node of alleged 0.5um points to is brake pole (the transistor that Gate) length is 0.5um. But, as the development of the times, the definition of technical node also is changing, nowadays is the measure index of the body related transistor no longer, is the name of the acting border of component pointing to era only. But, as node small shrink development, people never has been changed to raising the function of component and power, target that cuts manufacturing cost.
 
Of transistor small shrink problem

Picture out: Mynavi)
 
High-powered transistor was achieved in 20nm node around small the limit that shrink. The engineers of semiconductor industry must explore the method of other design transistor, because if narrow plane (Planar) the horizontal size of transistor, will produce other issue.
 
Three-dimensional FinFET (transistor of effect of fin type field) the structure, of transistor basically make element appearance stereoer to silicon brilliant circle, because this won’t reduce the raceway groove of transistor (Channel) capacity, narrow the interface of component is accumulated however (Footprint) . With respect to FinFET small shrink, as the method that improves component performance, it is the height that raising Fin commonly while, to increase every unit (Unit) the component density of the area and contractible horizontal size.
 
To maintain transistor small shrink, and the cell that obtains high-powered, low power comsumption, low cost, the method that implements in recent years is germanium is added in past silicon (Germanium) , but the node that should surmount 5nm with FinFET technology, still need new material! In addition, rice of the accept that press a layer board (Nano Sheet) , accept rice line (Nano Wire) wait for new material to make new solution very likely. Want to undertake machining to these new material, without doubt, small shrinking is must, and use atomic layer level neatly into film and etch craft is must.
 
Of transistor small shrink problem
(picture out: Mynavi)
 
Contact (Contact) of the layer small shrink (Scaling)
If narrow the dimension of transistor, for the join transistor, layer that discharge a line, with respect to need whole narrows contact (Contact) the dimension of the layer. Contact as the progress of acting border and local interior (Inter-connect) density is higher and higher, if be advanced further small the development that shrink, the cupreous layout of the mainstream will face serious task nowadays. Say for example, if want to reduce the wide cut of layout, height further, criterion the resistor of cupreous layout will substantially heighten. The home is in semiconductor manufacturer to be applied neatly what can prevent cupreous pollution to have taller resistance again already is new hold back (Barrier) material, new gasket (Liner) material while, do one’s best is reduced hold back (Barrier) layer, gasket (Liner) the space of the layer. Another kind of possibility is to use a kind not to need to hold back (Barrier) the other metal of the layer will replace copper, perhaps use the alloy of other metal and copper.
 
 Of transistor small shrink problem
(picture out: Mynavi) 
 
Of memory semiconductor capacity small shrink (Scaling)- – namely the amplification of the capacity
Of the memory semiconductor capacity of 3D NAND small shrink (Scaling) be to pass the pile of perpendicular direction to come true. the structure with respect to memory semiconductor, unit (Cell) the number of plies of density and pile layer increases into scale ground. What earlier 3D NAND uses commonly is 24 tectonic chip, the chip of 128 96 layer, construction has been measured nowadays produce, because this predicts pile,number of plies will increase further. And, each need even, smooth, and be united in wedlock cheek by jowl with lower level, the task that brings because of this pile number of plies also increased.
 
The abidance of pile number of plies increases those who brought memory semiconductor capacity to expand, and the amplification of memory semiconductor capacity makes have taller depth to compare again (Aspect) memory aperture (of Memory Hole) etch, a flight of stairs (line of the definition of Staircase) graph, word (Word-line) the follow-up technology such as tungsten fill is more sophisticated. In addition, if raceway groove (Channel) length lengthens, electronic mobility can be restricted, affect the performance of equipment. At present, people is advancing the becoming with be applied important velar technology and etch craft comes cogent the development that advances new acting boundary.
 
 Of transistor small shrink problem
(picture out: Mynavi)
 
Collect
The most most advanced nowadays chip is without doubt up to now the most advanced component in the product of design, production, also be all previous is advanced via a few years of people small the immediate positive result that shrink. Of size of today’s contractible standard way, seek is fore-and-aft the function that the component of pile asks (Performance) with cost (Cost) the aggrandizement of manufacturer of facilities of the progress that because semiconductor produces equipment,the advantage meets, production and chip manufacturer.
 
Those who pass semiconductor is small shrink (Scaling) development, the our job, change that understood means of diligent, recreation, communication to obtain world-shaking. As reform (Innovation) directional, we expect “More Moore (continuance rub Er is mensurable) ” can go down continuously. Regard industry of the semiconductor that prop up as another when be able to develop directional —- – will various technologies are shirt-sleeve the “More Than Moore in various construction, system (new rub Er law, surmount rub Er is mensurable) ” strategy also suffers quite fix eyes upon.
 
Future, we need to advance above at the same time the progress of these two direction, but, should push implementation more intelligence (Smart) , more interconnection (Connected) society and must speed and function need are applied to more industries to mix in getting.
 
 
Avoid duty statement: The article is reprint an article, reprint this article purpose to depend on passing more information, the person that copyright puts in original work ‘s charge is all. If involve work copyright issue,article place uses video, picture, written language, contact please small make up undertake handling.

 
 

Leave a Reply

Your email address will not be published. Required fields are marked *