[introduction]The integrality of power source is to be the tension that acknowledges power source origin and end end and electric current to whether accord with demand. Power source integrality is quite important in the electronic product of nowadays, involve chip level, chip to enclose face of ply of the level, circuit and systematic level.

Normally, power source integrality is the concept of a whole, “This word communicated integrality ” the meaning of the following respects:

(1) comprehensive sex and comprehensive consideration: Integrality means each aspects in considering a system, circuitry of the design that includes power supply, power source, power source is delivered, power source management. It asks to want to have enough attention in whole system, ensure power source concerns key part to be able to work normally in place.

(2) hale sex: Integrality still covered a system to exterior the suiting that disturb and changes ability. A system that has integrality of good power supply can be below the influence of the adverse element such as interference of change of voltage wave motion, electric current, electromagnetism, still can maintain the stability of its function.

(The integral stability of 3) system: This term emphasized power source system serving as integral stability. This included the dependability in power supply respect, and it is normal to ensure whole system is in fall to be able to maintain its performance level with unusual situation.

(The maintenance of 4) function: Integrality still is involved ensure each functions of the system are below all sorts of conditions can be able to maintain. This included to be opposite all of electronic equipment, computer science department or other the equipment that counts power source, power source integrality matters to the dependability of these equipment and stability directly.

The integrality of power source is to be the tension that acknowledges power source origin and end end and electric current to whether accord with demand. Power source integrality is quite important in the electronic product of nowadays, involve chip level, chip to enclose face of ply of the level, circuit and systematic level.

Whether does the result of power source integrality satisfy a requirement, decide integratedly by 3 parts, namely power supply module, transmission method and the end that use phone. When we design power source circuit, it is low noise, low ripple to the requirement of power source, and output voltage is accurate, stable, can reduce interference as far as possible to introduce thereby.

Assure power source integrality, final it is the noise abundant quantity that ensures the chip that use phone [51] [xz2] . The abundant of power source noise measures calculative process to be as follows.

(The norms book of 1) chip can give a normative value, it is normally 5% ; Want to consider dc of stabilized voltage chip outputs an error, it is ± commonly 2.5% , accordingly extent of peak value of power source noise does not exceed ± 2.5% .

(The working voltage limits that 2) is like chip is 3.13~3.47V, voltage of output of line out of stabilized voltage chip is 3.3V, installation is in the output voltage after circuit board is 3.36V. The span of concessional voltage is 3.47-3.36=0.11V. Precision of output of stabilized voltage chip is ± 1% , namely 0.0336V of ± of 1%= of 3.36* ± . The noise of power source makes rich the quantity is 0.11-0.0336=0.0764V, namely 76.4mV.

When the noise abundant of computational power source is measured, the following needs to notice.

(1) how much is the outputs voltage exact value of stabilized voltage chip.

(2) of the working environment of power source is the environment that place of stabilized voltage chip recommends.

(3) laden circumstance is how, this is influential also to the output of stabilized voltage chip.

(4) power source noise can affect signal quality finally. And the noise origin on signal is power source noise not just, reflection, string together the signal integrality problem such as faze to also can be on signal overlay. Because this cannot make rich all noise,the requirement of the quantity is to pass the noise that increases power source output to come true.

(5) different voltage grade asks to power source noise also not appearance, less noise surplus jumps over voltage small. Imitate circuit is taller to power source requirement.

Final the power source that we ask the sink that using electric parts of an apparatus accepts good quality, we need all noise of plane of whole power source. To the noise origin of power source: The voltage that stabilized voltage chip outputs is not constant, can have certain ripple; Regulated power supply cannot answer the load rapid change to voltaic demand in real time. The frequency that regulated power supply answers is in commonly 200kHz less than, can do correct response, exceeded this frequency criterion to bring a foot to be in occurrence voltage to decline in the output weak point of power source; Electric current of laden transient state arises in impedance of impedance of power source method and ground method pressure fall; External interference.

Mention here ” electric current of laden transient state ” , this problem is not the power source module that outputs end by power source or place of power source chip arises, be produced by the laden change of oneself of the load that use phone however, because many number signal is in,this laden change is ” jump change ” be produced. Integrated circuit is by countless logistic doors circuit is comprised, we can regard main output unit as CMOS inverter, if pursue,13.1 are shown.

The voltaic sketch map that graph 13.1 CMOS outputs

Should controlling signal is a low n when, PMOS is opened above, right now output is tall n. The instant that open, VCC passes LVCC and R, to the input of chip B pin undertakes charging. Should controlling signal is a tall n when, the NMOS below is opened, what output right now is low n. The instant that open, the n that the input pin of chip B stores undertakes discharging through NMOS. When CMOS inverter outputs condition happening to change, has flowed electric current is metabolic electric current. Then, taking a line, over- aperture, planar layer and enclose (bond down-lead, cite a base) on the link component that waits for these to have inductance, meet the induction gives voltage. For example GND ground potential of the standard should be 0V, but the inductance of link component existence between chip and ground, give voltage VGND with respect to meeting induction, so on chip ” the ground ” potential by drive up, prep above 0V. If the graph is shown 13.2 times, when CMOS output signal arrives from low n at the same time when tall n switch, observation of the meeting on VCC loses the noise of voltage to, also can affect GND at the same time, cause an oscillation likely. When output signal arrives from tall n when low n switch, the noise that observation of the meeting on GND presses to a positive electricity, also can affect VCC at the same time, cause an oscillation likely.

The voltage of the power source that output of graph 13.2 CMOS alternates voltage is brought about and GND changes

A CMOS can cause such interference, if a lot of CMOS work at the same time, the interference that the parts of an apparatus that use phone causes to power source plane and GND ground level will be very serious. This is the pin as chip increasing, electric current is bigger and bigger, compositive degree cause higher and higher we must take power source integrality seriously very much.

(1) of chip compositive degree bigger and bigger, amount of chip interior transistor is larger and larger also; The door circuit with transistor internal composition combines machine of position of logistic defer line and other logic.

(2) exterior power source makes chip the foot offers in-house transistor node of power source of a common, cause power source noise to be delivered in chip interior necessarily when transistor condition is changed.

(3) in-house transistor job needs kernel clock or be exterior clock synchronism, but because in-house defer reachs each transistor cannot strict synchronism, cause partial transistor to complete state transition, another part may be in changeover condition, the power source noise that be in circuit of tall n door so can send the input share of other door circuit.

Analyse above the course, everybody also can understand very much, why to want to will go Ou capacitance stands by the power source pin of the parts of an apparatus that use phone to place.

Go Ou capacitance (Decoupling Capacitor) in be being used at power source system normally, the purpose is when those who provide pair of power source noise is short, high frequency answer, supply integrated circuit in order to keep stable power source tension (IC) or the other parts of an apparatus that use phone. Will go the argument that Ou capacitance sets the position that standing by the parts of an apparatus that use phone to have a few keys:

1.Reduce inductance effect: In circuitry of power source power supply, power supply cord and ground wire have certain inductance. When instantaneous of the parts of an apparatus that use phone needs big electricity, as a result of the existence of inductance, the meeting in circuit produces voltage drop, bring about voltage of power supply of the parts of an apparatus that use phone to drop. Go through be being placed around the parts of an apparatus that use phone Ou capacitance, instantaneous electricity can be provided in the instant that use phone, the voltage drop that quits inductance causes.

2.Reduce the impedance of power source loop: Go Ou capacitance is in high frequency on have inferior impedance. Will go Ou capacitance is placed around the parts of an apparatus that use phone, can reduce the total impedance of power source loop, make power source offers instantaneous more easily demand of high frequency electricity.

3.Reduce the transmission with fluctuant voltage: The voltage wave motion on road of power supply cord can travel along circuit. Through will going Ou capacitance stands by the parts of an apparatus that use phone, the transmission that can reduce voltage to fluctuate is apart from, ensure the parts of an apparatus that use phone obtains stabler power source voltage.

4.The smallest change the effect of power source noise to adjacent circuit: Go the noise that Ou capacitance can absorb power supply cord to go up, prevent noise to transmit adjacent circuit through power supply cord. The stability of this adjacent to maintaining circuit and function are crucial.

Accordingly, go to rise to the greastest extent the effect of Ou capacitance, it is placed to be near the parts of an apparatus that use phone normally, answer of demand in order to ensure quickly to instantaneous electric current, the smallest the influence of the inductance in changing power source system and resistor.

Small enclose what He Xiaorong is worth to go the main reason that Ou capacitance should stand by power source pin more and of these capacitance high frequency answer the character that transmits with electric current to concern.

High frequency answer: Small the capacitance that encloses He Xiaorong to be worth is had inside high frequency limits normally better answer character. Because the wavelengh of high frequency signal is short, the physical dimension of capacitance and inductance are lesser to the influence of its impedance. Accordingly, what small-sized capacitance can provide pair of high frequency noise more is effective go Ou.

Electric current transmits speed: Small enclosed capacitance has inferior equivalent inductance normally, make its can transmit electricity quickly. Below high frequency circumstance, electric current needs to answer the demand of the parts of an apparatus that use phone quickly. Stand by power source pin through will small electric capacity, can reduce the inductance of voltaic method, answer ability what raise requirement of pair of instantaneous electric current quickly.

The local treatment of power source noise: The capacitance that Xiaorong is worth basically is used at processing local, the high frequency noise of instantaneous. Through approaching these electric capacity power source pin, the place that can introduce circuit board or chip in power source is offerred go immediately Ou effect, is not in further position. This conduces to the power source stability that maintains the parts of an apparatus that use phone, reduce the effect of pair of whole circuit.

Use small enclose what He Xiaorong is worth to go Ou capacitance stands by power source pin, conduce to optimize high frequency noise to go Ou effect, answer what provide pair of instantaneous electricity demand quickly. Such design conduces to the stability that maintains the parts of an apparatus that use phone and function.

With the example that a capacitance sets. The electric capacity that this combination uses is: Capacitance of 2 680uf Tantalum, capacitance of 7 2.2uf pottery and porcelain (0805 enclose) , capacitance of 13 0.22uf pottery and porcelain (0603 enclose) , capacitance of 26 0.022uf pottery and porcelain (0402) . The curve of evenness of the upside in the graph is the impedance curve of 680uf capacitance, other allows the curve of the value 3 times to be curve of word of 3 V in be a graph, from left to → 0.022uf of → 0.22uf of right 2.2uf. Total impedance curve is line of bottom thick Bao Lu.

This combination came true to arrive in 500K inside 150M limits maintain impedance to be under Europe of 33 fine long hair, reach 500M point, impedance rises to Europe of 110 fine long hair, see antiresonance nod pilot from inside the graph very low.

(origin: Hardware 100 thousand why)

 

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